DSP
Pipelined CORDIC atan2 engine for fixed-point vector phase estimation.
Radix-2 batch FFT compute core for fixed-size frame transforms.
True dual-port RAM abstraction used by FFT pipeline memories.
Audio DDS oscillator with explicit Gowin multiplier-backed gain.
Time-division polyphonic audio synth for register-controlled board designs.
Four TDM LFOs sharing one 4-page, 512-point half-period wavetable. The
TDM four-oscillator mono-to-stereo pan/mix stage.
Four phase-accumulator oscillators sharing one loadable 16-bit wavetable and
TDM global stereo balance/pan stage using one explicit Gowin multiplier.
Stereo cascaded biquad EQ for audio streams.
Portable stereo fixed-point gain stage for audio sample streams.
Shared stereo pan, global EQ, and output gain pipeline.
Register-controlled AXI-stream AM IQ demodulator.
Register-controlled AXI-stream AM IQ modulator.
Multi-channel AXI-stream biquad IIR filter.
AXI-stream numerically controlled oscillator and direct digital synthesis source.
AXI-stream FFT-bin product stage for spectral comparison pipelines.
AXI-stream spectral fingerprint extraction core.
AXI-stream fingerprint matcher for spectral feature vectors.
Multi-channel AXI-stream FIR filter.
AXI-stream fixed-point to floating-point conversion stage.
AXI-stream floating-point to fixed-point conversion stage.
AXI-stream frame statistics accumulator.
Multi-channel AXI-stream fixed-point gain stage.
AXI-stream complex magnitude-squared stage for IQ samples.
AXI-stream matrix/vector dot-product accelerator.
AXI-stream elementwise matrix arithmetic block.
Two-input AXI-stream mixer for fixed-point sample lanes.
AXI-stream one-pole low-pass filter.
Top-level AXI-stream RadFFT block.
Batch-oriented AXI-stream RadFFT implementation.
DDR-backed AXI-stream RadFFT accelerator.
Iterative AXI-stream RadFFT engine.
Eight-lane parallel AXI-stream RadFFT engine.
Radix-2 true-dual-port-memory AXI-stream RadFFT engine.
Radix-4 true-dual-port-memory AXI-stream RadFFT engine.
Streaming AXI-stream RadFFT architecture.
AXI-stream wrapper around the fixed-point CORDIC atan2 engine.
AXI-stream wrapper around the radix-2 batch FFT core.
Lookup ROM for FFT twiddle factors used by RadDSP FFT implementations.
Gowin GW5A 16-bit simple dual-port BSRAM wrapper.
Signed 27x18 multiply backed by the Gowin GW5A MULTALU27X18 primitive.
Signed 27x32 multiply built from two Gowin GW5A MULTALU27X18 blocks.
ECP5 signed multiplier wrapper with the same handshake shape as the
Vendor selector for RadDSP signed multipliers.
Fully pipelined unsigned integer square-root core.
Vendor-selected sequential square helper backed by RAD hard multiplier wrappers.
Vendor-selected wide signed multiplier built from the RAD hard multiplier wrapper.
DSP48-backed signed multiplier wrapper for Xilinx FPGA targets.
Sequential DSP48 square helper for Xilinx FPGA targets.
Wide signed multiplication helper built from Xilinx DSP48 resources.
AXI-stream wrapper around the Zadoff-Chu chirp frame detector.
Zadoff-Chu chirp frame detector for packet and burst synchronization.
Streaming Zadoff-Chu cross-correlator primitive.
Peak selection stage for Zadoff-Chu correlation results.
Debug
RADIF-accessible debug hub for the RadILA capture engine.
Integrated logic analyzer capture core for RadHDL debug builds.
Gowin GW5A DPB-backed dual-clock capture RAM for RadILA.
Interfaces
AXI4 memory-mapped to AXI-stream DMA bridge for RadIF systems.
AXI4-Lite slave bridge to the RadIF register transaction interface.
RADIF-controlled GPIO register block for simple board control and status.
I2C byte-register slave for simple board-control buses.
I2C slave bridge to the RadIF register transaction interface.
Bidirectional I2S to AXI-Stream bridge.
RADIF-controlled interrupt aggregator.
QSPI slave bridge to the RadIF register transaction interface.
Configurable RadIF register bank with software-visible storage.
RadIF register interconnect for routing one host interface to multiple register banks.
Register-controlled I2C master.
Register-controlled SPI master.
16-bit SMI-style parallel management interface bridge to RadIF registers.
SPI-controlled AXI master bridge.
SPI slave bridge to the RadIF register transaction interface.
UART bridge to the RADIF register interface for low-cost board bring-up.
Primitives
Multi-bit synchronizer for independently changing static/status bits.
Async-assert, sync-deassert reset synchronizer.
Gray-coded multi-bit CDC. The source input must change by one bit per
Two-phase valid/ready handshake CDC for a source-held payload.
Pulse transfer using a source-domain toggle and destination-domain edge
Single-bit clock-domain synchronizer.
Synchronous reset synchronizer. Assertion and deassertion are sampled by
RAD-owned VHDL vector wrapper around one ECP5 DP16KD configured as
RAD-owned VHDL vector wrapper around the ECP5 MULT18X18D hard multiplier.
Public vendor-neutral FIFO primitive.
Vendor-selected separate-clock FIFO with XPM-compatible ports.
RAD separate-clock FIFO built from explicit vendor RAM wrappers and Gray
RAD synchronous FIFO built from explicit vendor RAM wrappers plus local
Vendor-selected synchronous FIFO with XPM-compatible ports. Portable cores
Gowin separate-clock FIFO wrapper.
Gowin synchronous FIFO wrapper.
Lattice MachXO2/MachXO3 FIFO8KB primitive wrapper.
Public Lattice RAM wrapper. Internally delegates to the explicit DP16KD
ECP5 true dual-port RAM wrapper backed by explicit DP16KD blocks.
Public vendor-neutral RAM primitive.
Signed sample RAM wrapper for one write port and one read port.
Xilinx asynchronous FIFO wrapper. XPM imports stay isolated here.
Xilinx synchronous FIFO wrapper. XPM imports stay isolated here.
Xilinx RAM wrapper. XPM imports stay isolated here so portable cores can