Radical Computer Technologies
Primitives / entity

radhdl_ecp5_mult18x18d

Documentation version: 0.2.2-beta.1 / Subpackage: primitive_dsp / Source package: radprimitive

RAD-owned VHDL vector wrapper around the ECP5 MULT18X18D hard multiplier. The public ports match raddsp_lattice_mul's tiled multiplier needs.

Use Cases

Block Diagram

radhdl_ecp5_mult18x18d radhdl entity clk rst ce a b p
VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component radhdl_ecp5_mult18x18d is
  port (
    clk : in std_logic;
    rst : in std_logic;
    ce : in std_logic;
    a : in std_logic_vector(17 downto 0);
    b : in std_logic_vector(17 downto 0);
    p : out std_logic_vector(35 downto 0)
  );
end component;

Direct Entity Instantiation

u_radhdl_ecp5_mult18x18d : entity radhdl.radhdl_ecp5_mult18x18d
  port map (
    clk => <clk_signal>,
    rst => <rst_signal>,
    ce  => <ce_signal>,
    a   => <a_signal>,
    b   => <b_signal>,
    p   => <p_signal>
  );

Generics

No generics declared.

Ports

NameDirectionTypeDescription
clkinstd_logic
rstinstd_logic
ceinstd_logic
ainstd_logic_vector(17 downto 0)
binstd_logic_vector(17 downto 0)
poutstd_logic_vector(35 downto 0)

Testbenches

No directly associated testbench was found.

Sources