Use Cases
- Reusable RadHDL building block for graph-generated FPGA systems.
Block Diagram
VHDL Include And Instantiation Template
File Header
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library radhdl;
-- Direct entity instantiation below does not require importing the entity name.Component Declaration
component radhdl_ecp5_mult18x18d is
port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
a : in std_logic_vector(17 downto 0);
b : in std_logic_vector(17 downto 0);
p : out std_logic_vector(35 downto 0)
);
end component;Direct Entity Instantiation
u_radhdl_ecp5_mult18x18d : entity radhdl.radhdl_ecp5_mult18x18d
port map (
clk => <clk_signal>,
rst => <rst_signal>,
ce => <ce_signal>,
a => <a_signal>,
b => <b_signal>,
p => <p_signal>
);Generics
No generics declared.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
| clk | in | std_logic | |
| rst | in | std_logic | |
| ce | in | std_logic | |
| a | in | std_logic_vector(17 downto 0) | |
| b | in | std_logic_vector(17 downto 0) | |
| p | out | std_logic_vector(35 downto 0) |
Testbenches
No directly associated testbench was found.
Sources
- common/hdl/ecp5/radhdl_ecp5_mult18x18d.vhd
