Radical Computer Technologies
Primitives / entity

rad_cdc_handshake

Documentation version: 0.2.2-beta.1 / Subpackage: primitive_cdc / Source package: radprimitive

Two-phase valid/ready handshake CDC for a source-held payload.

Use Cases

Block Diagram

rad_cdc_handshake radhdl entity src_clk src_rst src_valid_i src_data_i dest_clk dest_rst dest_ready_i src_ready_o dest_valid_o dest_data_o
VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component rad_cdc_handshake is
  generic (
    VENDOR : string := "generic";
    DATA_WIDTH : positive := 1;
    STAGES : positive := 2
  );
  port (
    src_clk : in std_logic;
    src_rst : in std_logic;
    src_valid_i : in std_logic;
    src_data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    src_ready_o : out std_logic;
    dest_clk : in std_logic;
    dest_rst : in std_logic;
    dest_valid_o : out std_logic;
    dest_data_o : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    dest_ready_i : in std_logic
  );
end component;

Direct Entity Instantiation

u_rad_cdc_handshake : entity radhdl.rad_cdc_handshake
  generic map (
    VENDOR     => "generic",
    DATA_WIDTH => 1,
    STAGES     => 2
  )
  port map (
    src_clk      => <src_clk_signal>,
    src_rst      => <src_rst_signal>,
    src_valid_i  => <src_valid_i_signal>,
    src_data_i   => <src_data_i_signal>,
    src_ready_o  => <src_ready_o_signal>,
    dest_clk     => <dest_clk_signal>,
    dest_rst     => <dest_rst_signal>,
    dest_valid_o => <dest_valid_o_signal>,
    dest_data_o  => <dest_data_o_signal>,
    dest_ready_i => <dest_ready_i_signal>
  );

Generics

NameTypeDefaultDescription
VENDORstring"generic"
DATA_WIDTHpositive1
STAGESpositive2

Ports

NameDirectionTypeDescription
src_clkinstd_logic
src_rstinstd_logic
src_valid_iinstd_logic
src_data_iinstd_logic_vector(DATA_WIDTH - 1 downto 0)
src_ready_ooutstd_logic
dest_clkinstd_logic
dest_rstinstd_logic
dest_valid_ooutstd_logic
dest_data_ooutstd_logic_vector(DATA_WIDTH - 1 downto 0)
dest_ready_iinstd_logic

Testbenches

No directly associated testbench was found.

Sources