radhdl_fifo_async

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component radhdl_fifo_async is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "7series";
    FIFO_READ_LATENCY : integer := 1;
    FIFO_WRITE_DEPTH : integer := 1024;
    RD_DATA_COUNT_WIDTH : integer := 1;
    READ_DATA_WIDTH : integer := 32;
    READ_MODE : string := "std";
    WRITE_DATA_WIDTH : integer := 32;
    WR_DATA_COUNT_WIDTH : integer := 1
  );
  port (
    almost_empty : out std_logic;
    almost_full : out std_logic;
    data_valid : out std_logic;
    dout : out std_logic_vector(READ_DATA_WIDTH - 1 downto 0);
    empty : out std_logic;
    full : out std_logic;
    rd_data_count : out std_logic_vector(RD_DATA_COUNT_WIDTH - 1 downto 0);
    wr_data_count : out std_logic_vector(WR_DATA_COUNT_WIDTH - 1 downto 0);
    din : in std_logic_vector(WRITE_DATA_WIDTH - 1 downto 0);
    rd_clk : in std_logic;
    rd_en : in std_logic;
    rst : in std_logic;
    wr_clk : in std_logic;
    wr_en : in std_logic
  );
end component;

Direct Entity Instantiation

u_radhdl_fifo_async : entity radhdl.radhdl_fifo_async
  generic map (
    VENDOR              => "xilinx",
    DEVICE_FAMILY       => "7series",
    FIFO_READ_LATENCY   => 1,
    FIFO_WRITE_DEPTH    => 1024,
    RD_DATA_COUNT_WIDTH => 1,
    READ_DATA_WIDTH     => 32,
    READ_MODE           => "std",
    WRITE_DATA_WIDTH    => 32,
    WR_DATA_COUNT_WIDTH => 1
  )
  port map (
    almost_empty  => <almost_empty_signal>,
    almost_full   => <almost_full_signal>,
    data_valid    => <data_valid_signal>,
    dout          => <dout_signal>,
    empty         => <empty_signal>,
    full          => <full_signal>,
    rd_data_count => <rd_data_count_signal>,
    wr_data_count => <wr_data_count_signal>,
    din           => <din_signal>,
    rd_clk        => <rd_clk_signal>,
    rd_en         => <rd_en_signal>,
    rst           => <rst_signal>,
    wr_clk        => <wr_clk_signal>,
    wr_en         => <wr_en_signal>
  );