radhdl_sample_ram

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component radhdl_sample_ram is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "7series";
    DATA_WIDTH : positive := 16;
    ADDR_WIDTH : positive := 10;
    DEPTH : positive := 1024
  );
  port (
    clk : in std_logic;
    wr_en : in std_logic;
    wr_addr : in unsigned(ADDR_WIDTH - 1 downto 0);
    wr_data : in signed(DATA_WIDTH - 1 downto 0);
    rd_addr : in unsigned(ADDR_WIDTH - 1 downto 0);
    rd_data : out signed(DATA_WIDTH - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_radhdl_sample_ram : entity radhdl.radhdl_sample_ram
  generic map (
    VENDOR        => "xilinx",
    DEVICE_FAMILY => "7series",
    DATA_WIDTH    => 16,
    ADDR_WIDTH    => 10,
    DEPTH         => 1024
  )
  port map (
    clk     => <clk_signal>,
    wr_en   => <wr_en_signal>,
    wr_addr => <wr_addr_signal>,
    wr_data => <wr_data_signal>,
    rd_addr => <rd_addr_signal>,
    rd_data => <rd_data_signal>
  );