radhdl_ram

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component radhdl_ram is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "7series";
    MODE : string := "tdp";
    MEMORY_KIND : string := "bram";
    DATA_WIDTH : positive := 18;
    ADDR_WIDTH : positive := 10;
    DEPTH : positive := 1024;
    CLOCKING_MODE : string := "common_clock";
    MEMORY_INIT_FILE : string := "none";
    USE_MEM_INIT : integer := 0;
    SIMULATION : boolean := false
  );
  port (
    clka : in std_logic;
    rsta : in std_logic;
    a_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
    a_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    a_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    a_we : in std_logic;
    clkb : in std_logic;
    rstb : in std_logic;
    b_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
    b_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    b_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    b_we : in std_logic
  );
end component;

Direct Entity Instantiation

u_radhdl_ram : entity radhdl.radhdl_ram
  generic map (
    VENDOR           => "xilinx",
    DEVICE_FAMILY    => "7series",
    MODE             => "tdp",
    MEMORY_KIND      => "bram",
    DATA_WIDTH       => 18,
    ADDR_WIDTH       => 10,
    DEPTH            => 1024,
    CLOCKING_MODE    => "common_clock",
    MEMORY_INIT_FILE => "none",
    USE_MEM_INIT     => 0,
    SIMULATION       => false
  )
  port map (
    clka   => <clka_signal>,
    rsta   => <rsta_signal>,
    a_addr => <a_addr_signal>,
    a_din  => <a_din_signal>,
    a_dout => <a_dout_signal>,
    a_we   => <a_we_signal>,
    clkb   => <clkb_signal>,
    rstb   => <rstb_signal>,
    b_addr => <b_addr_signal>,
    b_din  => <b_din_signal>,
    b_dout => <b_dout_signal>,
    b_we   => <b_we_signal>
  );