radhdl_xilinx_fifo_async

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component radhdl_xilinx_fifo_async is
  generic (
    DATA_WIDTH : positive := 32;
    FIFO_DEPTH : positive := 1024;
    READ_MODE : string := "std";
    FIFO_READ_LATENCY : integer := 1;
    COUNT_WIDTH : positive := 10
  );
  port (
    wr_clk : in std_logic;
    rd_clk : in std_logic;
    rst : in std_logic;
    wr_en : in std_logic;
    rd_en : in std_logic;
    din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    empty : out std_logic;
    full : out std_logic;
    data_valid : out std_logic
  );
end component;

Direct Entity Instantiation

u_radhdl_xilinx_fifo_async : entity radhdl.radhdl_xilinx_fifo_async
  generic map (
    DATA_WIDTH        => 32,
    FIFO_DEPTH        => 1024,
    READ_MODE         => "std",
    FIFO_READ_LATENCY => 1,
    COUNT_WIDTH       => 10
  )
  port map (
    wr_clk     => <wr_clk_signal>,
    rd_clk     => <rd_clk_signal>,
    rst        => <rst_signal>,
    wr_en      => <wr_en_signal>,
    rd_en      => <rd_en_signal>,
    din        => <din_signal>,
    dout       => <dout_signal>,
    empty      => <empty_signal>,
    full       => <full_signal>,
    data_valid => <data_valid_signal>
  );