Radical Computer Technologies
Primitives / entity

rad_cdc_gray

Documentation version: 0.2.2-beta.1 / Subpackage: primitive_cdc / Source package: radprimitive

Gray-coded multi-bit CDC. The source input must change by one bit per transfer; this wrapper synchronizes each bit into dest_clk.

Use Cases

Block Diagram

rad_cdc_gray radhdl entity dest_clk src_gray_i dest_gray_o
VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component rad_cdc_gray is
  generic (
    VENDOR : string := "generic";
    DATA_WIDTH : positive := 4;
    STAGES : positive := 2
  );
  port (
    dest_clk : in std_logic;
    src_gray_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    dest_gray_o : out std_logic_vector(DATA_WIDTH - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_rad_cdc_gray : entity radhdl.rad_cdc_gray
  generic map (
    VENDOR     => "generic",
    DATA_WIDTH => 4,
    STAGES     => 2
  )
  port map (
    dest_clk    => <dest_clk_signal>,
    src_gray_i  => <src_gray_i_signal>,
    dest_gray_o => <dest_gray_o_signal>
  );

Generics

NameTypeDefaultDescription
VENDORstring"generic"
DATA_WIDTHpositive4
STAGESpositive2

Ports

NameDirectionTypeDescription
dest_clkinstd_logic
src_gray_iinstd_logic_vector(DATA_WIDTH - 1 downto 0)
dest_gray_ooutstd_logic_vector(DATA_WIDTH - 1 downto 0)

Testbenches

No directly associated testbench was found.

Sources