radhdl_ecp5_dp16kd_18x1024

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component radhdl_ecp5_dp16kd_18x1024 is
  port (
    clka : in std_logic;
    wea : in std_logic;
    addra : in std_logic_vector(9 downto 0);
    dia : in std_logic_vector(17 downto 0);
    doa : out std_logic_vector(17 downto 0);
    clkb : in std_logic;
    web : in std_logic;
    addrb : in std_logic_vector(9 downto 0);
    dib : in std_logic_vector(17 downto 0);
    dob : out std_logic_vector(17 downto 0)
  );
end component;

Direct Entity Instantiation

u_radhdl_ecp5_dp16kd_18x1024 : entity radhdl.radhdl_ecp5_dp16kd_18x1024
  port map (
    clka  => <clka_signal>,
    wea   => <wea_signal>,
    addra => <addra_signal>,
    dia   => <dia_signal>,
    doa   => <doa_signal>,
    clkb  => <clkb_signal>,
    web   => <web_signal>,
    addrb => <addrb_signal>,
    dib   => <dib_signal>,
    dob   => <dob_signal>
  );