radhdl_gowin_fifo_sc_sync

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component radhdl_gowin_fifo_sc_sync is
  generic (
    DATA_WIDTH : positive := 32;
    COUNT_WIDTH : positive := 10
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    wr_en : in std_logic;
    rd_en : in std_logic;
    din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    empty : out std_logic;
    full : out std_logic;
    almost_empty : out std_logic;
    almost_full : out std_logic;
    data_valid : out std_logic;
    data_count : out std_logic_vector(COUNT_WIDTH - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_radhdl_gowin_fifo_sc_sync : entity radhdl.radhdl_gowin_fifo_sc_sync
  generic map (
    DATA_WIDTH  => 32,
    COUNT_WIDTH => 10
  )
  port map (
    clk          => <clk_signal>,
    rst          => <rst_signal>,
    wr_en        => <wr_en_signal>,
    rd_en        => <rd_en_signal>,
    din          => <din_signal>,
    dout         => <dout_signal>,
    empty        => <empty_signal>,
    full         => <full_signal>,
    almost_empty => <almost_empty_signal>,
    almost_full  => <almost_full_signal>,
    data_valid   => <data_valid_signal>,
    data_count   => <data_count_signal>
  );