radhdl_fifo_bram_async

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component radhdl_fifo_bram_async is
  generic (
    VENDOR : string := "generic";
    DEVICE_FAMILY : string := "generic";
    DATA_WIDTH : positive := 32;
    ADDR_WIDTH : positive := 4;
    DEPTH : positive := 16;
    CDC_STAGES : positive := 2;
    SIMULATION : boolean := false
  );
  port (
    wr_clk : in std_logic;
    rd_clk : in std_logic;
    rst : in std_logic;
    wr_en : in std_logic;
    rd_en : in std_logic;
    din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    empty : out std_logic;
    full : out std_logic;
    data_valid : out std_logic;
    wr_data_count : out unsigned(ADDR_WIDTH downto 0);
    rd_data_count : out unsigned(ADDR_WIDTH downto 0)
  );
end component;

Direct Entity Instantiation

u_radhdl_fifo_bram_async : entity radhdl.radhdl_fifo_bram_async
  generic map (
    VENDOR        => "generic",
    DEVICE_FAMILY => "generic",
    DATA_WIDTH    => 32,
    ADDR_WIDTH    => 4,
    DEPTH         => 16,
    CDC_STAGES    => 2,
    SIMULATION    => false
  )
  port map (
    wr_clk        => <wr_clk_signal>,
    rd_clk        => <rd_clk_signal>,
    rst           => <rst_signal>,
    wr_en         => <wr_en_signal>,
    rd_en         => <rd_en_signal>,
    din           => <din_signal>,
    dout          => <dout_signal>,
    empty         => <empty_signal>,
    full          => <full_signal>,
    data_valid    => <data_valid_signal>,
    wr_data_count => <wr_data_count_signal>,
    rd_data_count => <rd_data_count_signal>
  );