radhdl_fifo_sync

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component radhdl_fifo_sync is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "7series";
    CASCADE_HEIGHT : integer := 0;
    DOUT_RESET_VALUE : string := "0";
    ECC_MODE : string := "no_ecc";
    FIFO_MEMORY_TYPE : string := "auto";
    FIFO_READ_LATENCY : integer := 1;
    FIFO_WRITE_DEPTH : integer := 1024;
    FULL_RESET_VALUE : integer := 0;
    PROG_EMPTY_THRESH : integer := 10;
    PROG_FULL_THRESH : integer := 10;
    RD_DATA_COUNT_WIDTH : integer := 1;
    READ_DATA_WIDTH : integer := 32;
    READ_MODE : string := "std";
    SIM_ASSERT_CHK : integer := 0;
    USE_ADV_FEATURES : string := "0707";
    WAKEUP_TIME : integer := 0;
    WRITE_DATA_WIDTH : integer := 32;
    WR_DATA_COUNT_WIDTH : integer := 1
  );
  port (
    almost_empty : out std_logic;
    almost_full : out std_logic;
    data_valid : out std_logic;
    dbiterr : out std_logic;
    dout : out std_logic_vector(READ_DATA_WIDTH - 1 downto 0);
    empty : out std_logic;
    full : out std_logic;
    overflow : out std_logic;
    prog_empty : out std_logic;
    prog_full : out std_logic;
    rd_data_count : out std_logic_vector(RD_DATA_COUNT_WIDTH - 1 downto 0);
    rd_rst_busy : out std_logic;
    sbiterr : out std_logic;
    underflow : out std_logic;
    wr_ack : out std_logic;
    wr_data_count : out std_logic_vector(WR_DATA_COUNT_WIDTH - 1 downto 0);
    wr_rst_busy : out std_logic;
    din : in std_logic_vector(WRITE_DATA_WIDTH - 1 downto 0);
    injectdbiterr : in std_logic;
    injectsbiterr : in std_logic;
    rd_en : in std_logic;
    rst : in std_logic;
    sleep : in std_logic;
    wr_clk : in std_logic;
    wr_en : in std_logic
  );
end component;

Direct Entity Instantiation

u_radhdl_fifo_sync : entity radhdl.radhdl_fifo_sync
  generic map (
    VENDOR              => "xilinx",
    DEVICE_FAMILY       => "7series",
    CASCADE_HEIGHT      => 0,
    DOUT_RESET_VALUE    => "0",
    ECC_MODE            => "no_ecc",
    FIFO_MEMORY_TYPE    => "auto",
    FIFO_READ_LATENCY   => 1,
    FIFO_WRITE_DEPTH    => 1024,
    FULL_RESET_VALUE    => 0,
    PROG_EMPTY_THRESH   => 10,
    PROG_FULL_THRESH    => 10,
    RD_DATA_COUNT_WIDTH => 1,
    READ_DATA_WIDTH     => 32,
    READ_MODE           => "std",
    SIM_ASSERT_CHK      => 0,
    USE_ADV_FEATURES    => "0707",
    WAKEUP_TIME         => 0,
    WRITE_DATA_WIDTH    => 32,
    WR_DATA_COUNT_WIDTH => 1
  )
  port map (
    almost_empty  => <almost_empty_signal>,
    almost_full   => <almost_full_signal>,
    data_valid    => <data_valid_signal>,
    dbiterr       => <dbiterr_signal>,
    dout          => <dout_signal>,
    empty         => <empty_signal>,
    full          => <full_signal>,
    overflow      => <overflow_signal>,
    prog_empty    => <prog_empty_signal>,
    prog_full     => <prog_full_signal>,
    rd_data_count => <rd_data_count_signal>,
    rd_rst_busy   => <rd_rst_busy_signal>,
    sbiterr       => <sbiterr_signal>,
    underflow     => <underflow_signal>,
    wr_ack        => <wr_ack_signal>,
    wr_data_count => <wr_data_count_signal>,
    wr_rst_busy   => <wr_rst_busy_signal>,
    din           => <din_signal>,
    injectdbiterr => <injectdbiterr_signal>,
    injectsbiterr => <injectsbiterr_signal>,
    rd_en         => <rd_en_signal>,
    rst           => <rst_signal>,
    sleep         => <sleep_signal>,
    wr_clk        => <wr_clk_signal>,
    wr_en         => <wr_en_signal>
  );