Radical Computer Technologies
Primitives / entity

rad_cdc_pulse

Documentation version: 0.2.2-beta.1 / Subpackage: primitive_cdc / Source package: radprimitive

Pulse transfer using a source-domain toggle and destination-domain edge detection.

Use Cases

Block Diagram

rad_cdc_pulse radhdl entity src_clk src_rst src_pulse_i dest_clk dest_rst dest_pulse_o
VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component rad_cdc_pulse is
  generic (
    VENDOR : string := "generic";
    STAGES : positive := 2
  );
  port (
    src_clk : in std_logic;
    src_rst : in std_logic;
    src_pulse_i : in std_logic;
    dest_clk : in std_logic;
    dest_rst : in std_logic;
    dest_pulse_o : out std_logic
  );
end component;

Direct Entity Instantiation

u_rad_cdc_pulse : entity radhdl.rad_cdc_pulse
  generic map (
    VENDOR => "generic",
    STAGES => 2
  )
  port map (
    src_clk      => <src_clk_signal>,
    src_rst      => <src_rst_signal>,
    src_pulse_i  => <src_pulse_i_signal>,
    dest_clk     => <dest_clk_signal>,
    dest_rst     => <dest_rst_signal>,
    dest_pulse_o => <dest_pulse_o_signal>
  );

Generics

NameTypeDefaultDescription
VENDORstring"generic"
STAGESpositive2

Ports

NameDirectionTypeDescription
src_clkinstd_logic
src_rstinstd_logic
src_pulse_iinstd_logic
dest_clkinstd_logic
dest_rstinstd_logic
dest_pulse_ooutstd_logic

Testbenches

No directly associated testbench was found.

Sources