raddsp_lattice_mul

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_lattice_mul is
  generic (
    DEVICE_FAMILY : string := "ecp5";
    A_WIDTH : positive := 16;
    B_WIDTH : positive := 18;
    SIMULATION : boolean := false
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    valid_i : in std_logic;
    subtract_i : in std_logic;
    last_i : in std_logic;
    a_i : in signed(A_WIDTH - 1 downto 0);
    b_i : in signed(B_WIDTH - 1 downto 0);
    valid_o : out std_logic;
    subtract_o : out std_logic;
    last_o : out std_logic;
    p_o : out signed(47 downto 0)
  );
end component;

Direct Entity Instantiation

u_raddsp_lattice_mul : entity radhdl.raddsp_lattice_mul
  generic map (
    DEVICE_FAMILY => "ecp5",
    A_WIDTH       => 16,
    B_WIDTH       => 18,
    SIMULATION    => false
  )
  port map (
    clk        => <clk_signal>,
    rst        => <rst_signal>,
    valid_i    => <valid_i_signal>,
    subtract_i => <subtract_i_signal>,
    last_i     => <last_i_signal>,
    a_i        => <a_i_signal>,
    b_i        => <b_i_signal>,
    valid_o    => <valid_o_signal>,
    subtract_o => <subtract_o_signal>,
    last_o     => <last_o_signal>,
    p_o        => <p_o_signal>
  );