Radical Computer Technologies
Primitives / entity

rad_cdc_single

Documentation version: 0.2.2-beta.1 / Subpackage: primitive_cdc / Source package: radprimitive

Single-bit clock-domain synchronizer.

Use Cases

Block Diagram

rad_cdc_single radhdl entity dest_clk src_i dest_o
VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component rad_cdc_single is
  generic (
    VENDOR : string := "generic";
    STAGES : positive := 2;
    INIT : std_logic := '0'
  );
  port (
    dest_clk : in std_logic;
    src_i : in std_logic;
    dest_o : out std_logic
  );
end component;

Direct Entity Instantiation

u_rad_cdc_single : entity radhdl.rad_cdc_single
  generic map (
    VENDOR => "generic",
    STAGES => 2,
    INIT   => '0'
  )
  port map (
    dest_clk => <dest_clk_signal>,
    src_i    => <src_i_signal>,
    dest_o   => <dest_o_signal>
  );

Generics

NameTypeDefaultDescription
VENDORstring"generic"
STAGESpositive2
INITstd_logic'0'

Ports

NameDirectionTypeDescription
dest_clkinstd_logic
src_iinstd_logic
dest_ooutstd_logic

Testbenches

No directly associated testbench was found.

Sources