Radical Computer Technologies
Primitives / entity

rad_cdc_async_rst

Documentation version: 0.2.2-beta.1 / Subpackage: primitive_cdc / Source package: radprimitive

Async-assert, sync-deassert reset synchronizer.

Use Cases

Block Diagram

rad_cdc_async_rst radhdl entity dest_clk rst_i rst_o
VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component rad_cdc_async_rst is
  generic (
    VENDOR : string := "generic";
    STAGES : positive := 2;
    ACTIVE_HIGH : boolean := true
  );
  port (
    dest_clk : in std_logic;
    rst_i : in std_logic;
    rst_o : out std_logic
  );
end component;

Direct Entity Instantiation

u_rad_cdc_async_rst : entity radhdl.rad_cdc_async_rst
  generic map (
    VENDOR      => "generic",
    STAGES      => 2,
    ACTIVE_HIGH => true
  )
  port map (
    dest_clk => <dest_clk_signal>,
    rst_i    => <rst_i_signal>,
    rst_o    => <rst_o_signal>
  );

Generics

NameTypeDefaultDescription
VENDORstring"generic"
STAGESpositive2
ACTIVE_HIGHbooleantrue

Ports

NameDirectionTypeDescription
dest_clkinstd_logic
rst_iinstd_logic
rst_ooutstd_logic

Testbenches

No directly associated testbench was found.

Sources