File Header
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
Component Declaration
component radhdl_lattice_fifo8kb is
generic (
DATA_WIDTH : positive := 18
);
port (
wr_clk : in std_logic;
rd_clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
rd_en : in std_logic;
din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
empty : out std_logic;
full : out std_logic;
almost_empty : out std_logic;
almost_full : out std_logic;
data_valid : out std_logic
);
end component;
Direct Entity Instantiation
u_radhdl_lattice_fifo8kb : entity radhdl.radhdl_lattice_fifo8kb
generic map (
DATA_WIDTH => 18
)
port map (
wr_clk => <wr_clk_signal>,
rd_clk => <rd_clk_signal>,
rst => <rst_signal>,
wr_en => <wr_en_signal>,
rd_en => <rd_en_signal>,
din => <din_signal>,
dout => <dout_signal>,
empty => <empty_signal>,
full => <full_signal>,
almost_empty => <almost_empty_signal>,
almost_full => <almost_full_signal>,
data_valid => <data_valid_signal>
);