Radical Computer Technologies
Primitives / entity

radhdl_lattice_fifo8kb

Documentation version: 0.2.2-beta.1 / Subpackage: primitive_fifo / Source package: radprimitive

Lattice MachXO2/MachXO3 FIFO8KB primitive wrapper. This is intentionally a primitive wrapper, not a RAM-inferred FIFO.

Use Cases

Block Diagram

radhdl_lattice_fifo8kb radhdl entity wr_clk rd_clk rst wr_en rd_en din dout empty full almost_empty almost_full data_valid
VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.

Component Declaration

component radhdl_lattice_fifo8kb is
  generic (
    DATA_WIDTH : positive := 18
  );
  port (
    wr_clk : in std_logic;
    rd_clk : in std_logic;
    rst : in std_logic;
    wr_en : in std_logic;
    rd_en : in std_logic;
    din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    empty : out std_logic;
    full : out std_logic;
    almost_empty : out std_logic;
    almost_full : out std_logic;
    data_valid : out std_logic
  );
end component;

Direct Entity Instantiation

u_radhdl_lattice_fifo8kb : entity radhdl.radhdl_lattice_fifo8kb
  generic map (
    DATA_WIDTH => 18
  )
  port map (
    wr_clk       => <wr_clk_signal>,
    rd_clk       => <rd_clk_signal>,
    rst          => <rst_signal>,
    wr_en        => <wr_en_signal>,
    rd_en        => <rd_en_signal>,
    din          => <din_signal>,
    dout         => <dout_signal>,
    empty        => <empty_signal>,
    full         => <full_signal>,
    almost_empty => <almost_empty_signal>,
    almost_full  => <almost_full_signal>,
    data_valid   => <data_valid_signal>
  );

Generics

NameTypeDefaultDescription
DATA_WIDTHpositive18

Ports

NameDirectionTypeDescription
wr_clkinstd_logic
rd_clkinstd_logic
rstinstd_logic
wr_eninstd_logic
rd_eninstd_logic
dininstd_logic_vector(DATA_WIDTH - 1 downto 0)
doutoutstd_logic_vector(DATA_WIDTH - 1 downto 0)
emptyoutstd_logic
fulloutstd_logic
almost_emptyoutstd_logic
almost_fulloutstd_logic
data_validoutstd_logic

Register Interfaces

No fixed register map was found; this section documents the exposed register/control interface ports.

InterfaceDirectionsSignalsRepresentative ports
Register control/statusin4wr_clk, rd_clk, wr_en, rd_en

Testbenches

No directly associated testbench was found.

Sources