raddsp_square_seq

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_square_seq is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "7series";
    WIDTH : positive := 32
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    start_i : in std_logic;
    x_i : in signed(WIDTH - 1 downto 0);
    busy_o : out std_logic;
    valid_o : out std_logic;
    y_o : out unsigned((2 * WIDTH) - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_raddsp_square_seq : entity radhdl.raddsp_square_seq
  generic map (
    VENDOR        => "xilinx",
    DEVICE_FAMILY => "7series",
    WIDTH         => 32
  )
  port map (
    clk     => <clk_signal>,
    rst     => <rst_signal>,
    start_i => <start_i_signal>,
    x_i     => <x_i_signal>,
    busy_o  => <busy_o_signal>,
    valid_o => <valid_o_signal>,
    y_o     => <y_o_signal>
  );