DSP
Pipelined CORDIC atan2 engine for fixed-point vector phase estimation.
Radix-2 batch FFT compute core for fixed-size frame transforms.
True dual-port RAM abstraction used by FFT pipeline memories.
Register-controlled AXI-stream AM IQ demodulator.
Register-controlled AXI-stream AM IQ modulator.
Multi-channel AXI-stream biquad IIR filter.
AXI-stream numerically controlled oscillator and direct digital synthesis source.
AXI-stream FFT-bin product stage for spectral comparison pipelines.
AXI-stream spectral fingerprint extraction core.
AXI-stream fingerprint matcher for spectral feature vectors.
Multi-channel AXI-stream FIR filter.
AXI-stream fixed-point to floating-point conversion stage.
AXI-stream floating-point to fixed-point conversion stage.
AXI-stream frame statistics accumulator.
Multi-channel AXI-stream fixed-point gain stage.
AXI-stream complex magnitude-squared stage for IQ samples.
AXI-stream matrix/vector dot-product accelerator.
AXI-stream elementwise matrix arithmetic block.
Two-input AXI-stream mixer for fixed-point sample lanes.
AXI-stream one-pole low-pass filter.
Top-level AXI-stream RadFFT block.
Batch-oriented AXI-stream RadFFT implementation.
DDR-backed AXI-stream RadFFT accelerator.
Iterative AXI-stream RadFFT engine.
Eight-lane parallel AXI-stream RadFFT engine.
Radix-2 true-dual-port-memory AXI-stream RadFFT engine.
Radix-4 true-dual-port-memory AXI-stream RadFFT engine.
Streaming AXI-stream RadFFT architecture.
AXI-stream wrapper around the fixed-point CORDIC atan2 engine.
AXI-stream wrapper around the radix-2 batch FFT core.
Lookup ROM for FFT twiddle factors used by RadDSP FFT implementations.
Fully pipelined unsigned integer square-root core.
DSP48-backed signed multiplier wrapper for Xilinx FPGA targets.
Sequential DSP48 square helper for Xilinx FPGA targets.
Wide signed multiplication helper built from Xilinx DSP48 resources.
AXI-stream wrapper around the Zadoff-Chu chirp frame detector.
Zadoff-Chu chirp frame detector for packet and burst synchronization.
Streaming Zadoff-Chu cross-correlator primitive.
Peak selection stage for Zadoff-Chu correlation results.
Debug
RADIF-accessible debug hub for the RadILA capture engine.
Integrated logic analyzer capture core for RadHDL debug builds.
Interfaces
AXI4 memory-mapped to AXI-stream DMA bridge for RadIF systems.
AXI4-Lite slave bridge to the RadIF register transaction interface.
RADIF-controlled GPIO register block for simple board control and status.
I2C slave bridge to the RadIF register transaction interface.
Bidirectional I2S to AXI-Stream bridge.
RADIF-controlled interrupt aggregator.
QSPI slave bridge to the RadIF register transaction interface.
Configurable RadIF register bank with software-visible storage.
RadIF register interconnect for routing one host interface to multiple register banks.
Register-controlled I2C master.
Register-controlled SPI master.
16-bit SMI-style parallel management interface bridge to RadIF registers.
SPI-controlled AXI master bridge.
SPI slave bridge to the RadIF register transaction interface.
UART bridge to the RADIF register interface for low-cost board bring-up.