cordic_atan2 Datasheet

Use Cases

Reusable FPGA DSP pipelines that need fixed-point, timing-aware implementation.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component cordic_atan2 is
  generic (
    G_INPUT_WIDTH : integer := 16;
    G_PHASE_WIDTH : integer := 32;
    G_ITERATIONS : integer := 24
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    input_valid : in std_logic;
    x_in : in signed(G_INPUT_WIDTH - 1 downto 0);
    y_in : in signed(G_INPUT_WIDTH - 1 downto 0);
    input_ready : out std_logic;
    busy : out std_logic;
    phase_valid : out std_logic;
    phase_out : out signed(G_PHASE_WIDTH - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_cordic_atan2 : entity radhdl.cordic_atan2
  generic map (
    G_INPUT_WIDTH => 16,
    G_PHASE_WIDTH => 32,
    G_ITERATIONS  => 24
  )
  port map (
    clk         => <clk_signal>,
    rst         => <rst_signal>,
    input_valid => <input_valid_signal>,
    x_in        => <x_in_signal>,
    y_in        => <y_in_signal>,
    input_ready => <input_ready_signal>,
    busy        => <busy_signal>,
    phase_valid => <phase_valid_signal>,
    phase_out   => <phase_out_signal>
  );

Generics

Name	Type	Default	Description
G_INPUT_WIDTH	integer	16	Sets the bit width for G INPUT WIDTH values carried by this module.
G_PHASE_WIDTH	integer	32	Sets the bit width for G PHASE WIDTH values carried by this module.
G_ITERATIONS	integer	24	Configures G ITERATIONS for this instance.

Ports

Name	Direction	Type	Description
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rst	in	std_logic	Active-high synchronous reset for this clock domain.
input_valid	in	std_logic	Input valid interface signal.
x_in	in	signed(G_INPUT_WIDTH - 1 downto 0)	X in interface signal.
y_in	in	signed(G_INPUT_WIDTH - 1 downto 0)	Y in interface signal.
input_ready	out	std_logic	Input ready interface signal.
busy	out	std_logic	Busy interface signal.
phase_valid	out	std_logic	Phase valid interface signal.
phase_out	out	signed(G_PHASE_WIDTH - 1 downto 0)	Phase out interface signal.

Testbenches

tb_cordic_atan2 captured waveform

Source: dsp/hdl/testbenches/tb_cordic_atan2.vhd

Self-checking or stimulus-focused testbench for cordic atan2. Exercises representative handshakes, reset behavior, frame boundaries, and numeric corner cases for regression runs.

Artifacts: status, vcd

Data Plots

CORDIC Atan2 Input Vectors

Signed X/Y vectors swept through the atan2 pipeline.

CORDIC Atan2 Phase Code

Unsigned phase accumulator code emitted by the CORDIC after pipeline latency.

Captured GHDL Waveform

Source: dsp/hdl/testbenches/tb_cordic_atan2.vhd

Horizontal Vertical

clk

rst

input_valid

x_in[15:0]

y_in[15:0]

input_ready

busy

phase_valid

phase_out[31:0]

valid_pipe[0:24]

Sources

dsp/hdl/raddsp/src/cordic_atan2.vhd