radif_axi_lite_to_reg

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_axi.all;

Component Declaration

component radif_axi_lite_to_reg is
  generic (
    DATA_WIDTH : integer := 32;
    ADDR_WIDTH : integer := 16;
    AXI_ADDR_WIDTH : integer := 16;
    VENDOR_TAG : string := "XILINX";
    PRODUCT_SERIES_TAG : string := "GENERIC"
  );
  port (
    s_axi_awaddr : in std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0);
    s_axi_awprot : in std_logic_vector(2 downto 0);
    s_axi_awvalid : in std_logic;
    s_axi_awready : out std_logic;
    s_axi_wdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    s_axi_wstrb : in std_logic_vector((DATA_WIDTH / 8) - 1 downto 0);
    s_axi_wvalid : in std_logic;
    s_axi_wready : out std_logic;
    s_axi_bresp : out std_logic_vector(1 downto 0);
    s_axi_bvalid : out std_logic;
    s_axi_bready : in std_logic;
    s_axi_araddr : in std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0);
    s_axi_arprot : in std_logic_vector(2 downto 0);
    s_axi_arvalid : in std_logic;
    s_axi_arready : out std_logic;
    s_axi_rdata : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    s_axi_rresp : out std_logic_vector(1 downto 0);
    s_axi_rvalid : out std_logic;
    s_axi_rready : in std_logic;
    clk : in std_logic;
    rstn : in std_logic;
    reg_wr_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
    reg_rd_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
    reg_wr_en : out std_logic;
    reg_rd_en : out std_logic;
    reg_data_in : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_wr_rdy : in std_logic;
    reg_rd_rdy : in std_logic;
    reg_wr_valid : in std_logic;
    reg_rd_valid : in std_logic;
    reg_error : in std_logic
  );
end component;

Direct Entity Instantiation

u_radif_axi_lite_to_reg : entity radhdl.radif_axi_lite_to_reg
  generic map (
    DATA_WIDTH         => 32,
    ADDR_WIDTH         => 16,
    AXI_ADDR_WIDTH     => 16,
    VENDOR_TAG         => "XILINX",
    PRODUCT_SERIES_TAG => "GENERIC"
  )
  port map (
    s_axi_awaddr  => <s_axi_awaddr_signal>,
    s_axi_awprot  => <s_axi_awprot_signal>,
    s_axi_awvalid => <s_axi_awvalid_signal>,
    s_axi_awready => <s_axi_awready_signal>,
    s_axi_wdata   => <s_axi_wdata_signal>,
    s_axi_wstrb   => <s_axi_wstrb_signal>,
    s_axi_wvalid  => <s_axi_wvalid_signal>,
    s_axi_wready  => <s_axi_wready_signal>,
    s_axi_bresp   => <s_axi_bresp_signal>,
    s_axi_bvalid  => <s_axi_bvalid_signal>,
    s_axi_bready  => <s_axi_bready_signal>,
    s_axi_araddr  => <s_axi_araddr_signal>,
    s_axi_arprot  => <s_axi_arprot_signal>,
    s_axi_arvalid => <s_axi_arvalid_signal>,
    s_axi_arready => <s_axi_arready_signal>,
    s_axi_rdata   => <s_axi_rdata_signal>,
    s_axi_rresp   => <s_axi_rresp_signal>,
    s_axi_rvalid  => <s_axi_rvalid_signal>,
    s_axi_rready  => <s_axi_rready_signal>,
    clk           => <clk_signal>,
    rstn          => <rstn_signal>,
    reg_wr_addr   => <reg_wr_addr_signal>,
    reg_rd_addr   => <reg_rd_addr_signal>,
    reg_wr_en     => <reg_wr_en_signal>,
    reg_rd_en     => <reg_rd_en_signal>,
    reg_data_in   => <reg_data_in_signal>,
    reg_data_out  => <reg_data_out_signal>,
    reg_wr_rdy    => <reg_wr_rdy_signal>,
    reg_rd_rdy    => <reg_rd_rdy_signal>,
    reg_wr_valid  => <reg_wr_valid_signal>,
    reg_rd_valid  => <reg_rd_valid_signal>,
    reg_error     => <reg_error_signal>
  );