fft_tdp_ram Datasheet

Use Cases

Reusable FPGA DSP pipelines that need fixed-point, timing-aware implementation.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component fft_tdp_ram is
  generic (
    DEVICE_FAMILY : string := "ultrascale+";
    MEMORY_STYLE : string := "block";
    DATA_WIDTH : integer := 64;
    ADDR_WIDTH : integer := 5;
    DEPTH : integer := 32
  );
  port (
    clk : in std_logic;
    a_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
    a_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    a_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    a_we : in std_logic;
    b_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
    b_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    b_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    b_we : in std_logic
  );
end component;

Direct Entity Instantiation

u_fft_tdp_ram : entity radhdl.fft_tdp_ram
  generic map (
    DEVICE_FAMILY => "ultrascale+",
    MEMORY_STYLE  => "block",
    DATA_WIDTH    => 64,
    ADDR_WIDTH    => 5,
    DEPTH         => 32
  )
  port map (
    clk    => <clk_signal>,
    a_addr => <a_addr_signal>,
    a_din  => <a_din_signal>,
    a_dout => <a_dout_signal>,
    a_we   => <a_we_signal>,
    b_addr => <b_addr_signal>,
    b_din  => <b_din_signal>,
    b_dout => <b_dout_signal>,
    b_we   => <b_we_signal>
  );

Generics

Name	Type	Default	Description
DEVICE_FAMILY	string	"ultrascale+"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.
MEMORY_STYLE	string	"block"	Configures MEMORY STYLE for this instance.
DATA_WIDTH	integer	64	Sets the bit width for DATA WIDTH values carried by this module.
ADDR_WIDTH	integer	5	Sets the bit width for ADDR WIDTH values carried by this module.
DEPTH	integer	32	Sets the storage depth, frame length, or number of buffered samples used internally.

Ports

Name	Direction	Type	Description
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
a_addr	in	std_logic_vector(ADDR_WIDTH - 1 downto 0)	A addr interface signal.
a_din	in	std_logic_vector(DATA_WIDTH - 1 downto 0)	A din interface signal.
a_dout	out	std_logic_vector(DATA_WIDTH - 1 downto 0)	A dout interface signal.
a_we	in	std_logic	A we interface signal.
b_addr	in	std_logic_vector(ADDR_WIDTH - 1 downto 0)	B addr interface signal.
b_din	in	std_logic_vector(DATA_WIDTH - 1 downto 0)	B din interface signal.
b_dout	out	std_logic_vector(DATA_WIDTH - 1 downto 0)	B dout interface signal.
b_we	in	std_logic	B we interface signal.

Testbenches

No directly associated testbench was found.

Sources

dsp/hdl/raddsp/src/fft_tdp_ram.vhd