radif_reg_interconnect

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_regbank.all;

Component Declaration

component radif_reg_interconnect is
  generic (
    DATA_WIDTH : integer := 32;
    ADDR_WIDTH : integer := 16;
    SLAVE_COUNT : integer := 2;
    SLAVE_BASE_ADDRS : std_logic_vector((SLAVE_COUNT * ADDR_WIDTH) - 1 downto 0) := x"00000000";
    SLAVE_ADDR_MASKS : std_logic_vector((SLAVE_COUNT * ADDR_WIDTH) - 1 downto 0) := x"F000F000";
    VENDOR_TAG : string := "XILINX";
    PRODUCT_SERIES_TAG : string := "GENERIC"
  );
  port (
    clk : in std_logic;
    rstn : in std_logic;
    wr_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
    rd_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
    wr_en_i : in std_logic;
    rd_en_i : in std_logic;
    data_in_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    data_out_o : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    wr_rdy_o : out std_logic;
    rd_rdy_o : out std_logic;
    wr_valid_o : out std_logic;
    rd_valid_o : out std_logic;
    error_o : out std_logic;
    s_wr_addr_o : out std_logic_vector((SLAVE_COUNT * ADDR_WIDTH) - 1 downto 0);
    s_rd_addr_o : out std_logic_vector((SLAVE_COUNT * ADDR_WIDTH) - 1 downto 0);
    s_wr_en_o : out std_logic_vector(SLAVE_COUNT - 1 downto 0);
    s_rd_en_o : out std_logic_vector(SLAVE_COUNT - 1 downto 0);
    s_data_in_o : out std_logic_vector((SLAVE_COUNT * DATA_WIDTH) - 1 downto 0);
    s_data_out_i : in std_logic_vector((SLAVE_COUNT * DATA_WIDTH) - 1 downto 0);
    s_wr_rdy_i : in std_logic_vector(SLAVE_COUNT - 1 downto 0);
    s_rd_rdy_i : in std_logic_vector(SLAVE_COUNT - 1 downto 0);
    s_wr_valid_i : in std_logic_vector(SLAVE_COUNT - 1 downto 0);
    s_rd_valid_i : in std_logic_vector(SLAVE_COUNT - 1 downto 0);
    s_error_i : in std_logic_vector(SLAVE_COUNT - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_radif_reg_interconnect : entity radhdl.radif_reg_interconnect
  generic map (
    DATA_WIDTH         => 32,
    ADDR_WIDTH         => 16,
    SLAVE_COUNT        => 2,
    SLAVE_BASE_ADDRS   => x"00000000",
    SLAVE_ADDR_MASKS   => x"F000F000",
    VENDOR_TAG         => "XILINX",
    PRODUCT_SERIES_TAG => "GENERIC"
  )
  port map (
    clk          => <clk_signal>,
    rstn         => <rstn_signal>,
    wr_addr_i    => <wr_addr_i_signal>,
    rd_addr_i    => <rd_addr_i_signal>,
    wr_en_i      => <wr_en_i_signal>,
    rd_en_i      => <rd_en_i_signal>,
    data_in_i    => <data_in_i_signal>,
    data_out_o   => <data_out_o_signal>,
    wr_rdy_o     => <wr_rdy_o_signal>,
    rd_rdy_o     => <rd_rdy_o_signal>,
    wr_valid_o   => <wr_valid_o_signal>,
    rd_valid_o   => <rd_valid_o_signal>,
    error_o      => <error_o_signal>,
    s_wr_addr_o  => <s_wr_addr_o_signal>,
    s_rd_addr_o  => <s_rd_addr_o_signal>,
    s_wr_en_o    => <s_wr_en_o_signal>,
    s_rd_en_o    => <s_rd_en_o_signal>,
    s_data_in_o  => <s_data_in_o_signal>,
    s_data_out_i => <s_data_out_i_signal>,
    s_wr_rdy_i   => <s_wr_rdy_i_signal>,
    s_rd_rdy_i   => <s_rd_rdy_i_signal>,
    s_wr_valid_i => <s_wr_valid_i_signal>,
    s_rd_valid_i => <s_rd_valid_i_signal>,
    s_error_i    => <s_error_i_signal>
  );