radif_smi16_to_reg Datasheet

Use Cases

Memory-mapped control/status integration with software-visible register maps.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_smi.all;

Component Declaration

component radif_smi16_to_reg is
  generic (
    DATA_WIDTH : integer := 32;
    REG_ADDR_WIDTH : integer := 16;
    SMI_ADDR_WIDTH : integer := 16;
    VENDOR_TAG : string := "XILINX";
    PRODUCT_SERIES_TAG : string := "GENERIC"
  );
  port (
    clk : in std_logic;
    rstn : in std_logic;
    smi_cs_n_i : in std_logic;
    smi_rd_n_i : in std_logic;
    smi_wr_n_i : in std_logic;
    smi_addr_i : in std_logic_vector(SMI_ADDR_WIDTH - 1 downto 0);
    smi_data_i : in std_logic_vector(15 downto 0);
    smi_data_o : out std_logic_vector(15 downto 0);
    smi_data_oen : out std_logic;
    smi_ack_o : out std_logic;
    reg_wr_addr : out std_logic_vector(REG_ADDR_WIDTH - 1 downto 0);
    reg_rd_addr : out std_logic_vector(REG_ADDR_WIDTH - 1 downto 0);
    reg_wr_en : out std_logic;
    reg_rd_en : out std_logic;
    reg_data_in : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_wr_rdy : in std_logic;
    reg_rd_rdy : in std_logic;
    reg_wr_valid : in std_logic;
    reg_rd_valid : in std_logic;
    reg_error : in std_logic
  );
end component;

Direct Entity Instantiation

u_radif_smi16_to_reg : entity radhdl.radif_smi16_to_reg
  generic map (
    DATA_WIDTH         => 32,
    REG_ADDR_WIDTH     => 16,
    SMI_ADDR_WIDTH     => 16,
    VENDOR_TAG         => "XILINX",
    PRODUCT_SERIES_TAG => "GENERIC"
  )
  port map (
    clk          => <clk_signal>,
    rstn         => <rstn_signal>,
    smi_cs_n_i   => <smi_cs_n_i_signal>,
    smi_rd_n_i   => <smi_rd_n_i_signal>,
    smi_wr_n_i   => <smi_wr_n_i_signal>,
    smi_addr_i   => <smi_addr_i_signal>,
    smi_data_i   => <smi_data_i_signal>,
    smi_data_o   => <smi_data_o_signal>,
    smi_data_oen => <smi_data_oen_signal>,
    smi_ack_o    => <smi_ack_o_signal>,
    reg_wr_addr  => <reg_wr_addr_signal>,
    reg_rd_addr  => <reg_rd_addr_signal>,
    reg_wr_en    => <reg_wr_en_signal>,
    reg_rd_en    => <reg_rd_en_signal>,
    reg_data_in  => <reg_data_in_signal>,
    reg_data_out => <reg_data_out_signal>,
    reg_wr_rdy   => <reg_wr_rdy_signal>,
    reg_rd_rdy   => <reg_rd_rdy_signal>,
    reg_wr_valid => <reg_wr_valid_signal>,
    reg_rd_valid => <reg_rd_valid_signal>,
    reg_error    => <reg_error_signal>
  );

Generics

Name	Type	Default	Description
DATA_WIDTH	integer	32	Sets the bit width for DATA WIDTH values carried by this module.
REG_ADDR_WIDTH	integer	16	Sets the bit width for REG ADDR WIDTH values carried by this module.
SMI_ADDR_WIDTH	integer	16	Sets the bit width for SMI ADDR WIDTH values carried by this module.
VENDOR_TAG	string	"XILINX"	Selects the vendor-specific implementation path, usually XILINX for DSP48/XPM-backed builds or generic for portable RTL.
PRODUCT_SERIES_TAG	string	"GENERIC"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.

Ports

Name	Direction	Type	Description
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rstn	in	std_logic	Active-low reset for this clock domain.
smi_cs_n_i	in	std_logic	Input smi cs n i signal for this module.
smi_rd_n_i	in	std_logic	Input smi rd n i signal for this module.
smi_wr_n_i	in	std_logic	Input smi wr n i signal for this module.
smi_addr_i	in	std_logic_vector(SMI_ADDR_WIDTH - 1 downto 0)	Input smi addr i signal for this module.
smi_data_i	in	std_logic_vector(15 downto 0)	Input smi data i signal for this module.
smi_data_o	out	std_logic_vector(15 downto 0)	Output smi data o signal generated by this module.
smi_data_oen	out	std_logic	Smi data oen interface signal.
smi_ack_o	out	std_logic	Output smi ack o signal generated by this module.
reg_wr_addr	out	std_logic_vector(REG_ADDR_WIDTH - 1 downto 0)	Register write address issued to the internal RadIF register target.
reg_rd_addr	out	std_logic_vector(REG_ADDR_WIDTH - 1 downto 0)	Register read address issued to the internal RadIF register target.
reg_wr_en	out	std_logic	One-cycle write request pulse for the internal register target.
reg_rd_en	out	std_logic	One-cycle read request pulse for the internal register target.
reg_data_in	out	std_logic_vector(DATA_WIDTH - 1 downto 0)	Write data presented to the internal register target.
reg_data_out	in	std_logic_vector(DATA_WIDTH - 1 downto 0)	Read data returned by the internal register target.
reg_wr_rdy	in	std_logic	Write-side ready indication from the internal register target.
reg_rd_rdy	in	std_logic	Read-side ready indication from the internal register target.
reg_wr_valid	in	std_logic	Write response valid indication from the internal register target.
reg_rd_valid	in	std_logic	Read response valid indication from the internal register target.
reg_error	in	std_logic	Register target error flag converted into the external bus error response.

Register Interfaces

No fixed register map was found; this section documents the exposed register/control interface ports.

Interface	Directions	Signals	Representative ports
Register control/status	in, out	13	smi_rd_n_i, smi_wr_n_i, reg_wr_addr, reg_rd_addr, reg_wr_en, reg_rd_en, reg_data_in, reg_data_out, +5 more

Testbenches

tb_radif_smi16_to_reg captured waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_smi16_to_reg.vhd

Self-checking or stimulus-focused testbench for smi16 to reg. Exercises representative handshakes, reset behavior, frame boundaries, and numeric corner cases for regression runs.

Artifacts: status, vcd

Captured GHDL Waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_smi16_to_reg.vhd

Horizontal Vertical

clk

rstn

cs_n

rd_n

wr_n

wr_addr[15:0]

rd_addr[15:0]

wr_en

rd_en

reg_din[63:0]

reg_dout[63:0]

wr_rdy

rd_rdy

wr_valid

rd_valid

reg_error

reg_wr_addr[15:0]

reg_rd_addr[15:0]

reg_wr_en

reg_rd_en

reg_data_in[63:0]

reg_data_out[63:0]

reg_wr_rdy

reg_rd_rdy

reg_wr_valid

reg_rd_valid

cs_meta

cs_sync

rd_meta

rd_sync

rd_prev

wr_meta

wr_sync

wr_prev

wr_addr_r[15:0]

rd_addr_r[15:0]

wr_data_r[63:0]

rd_cache_r[63:0]

rd_data_r[15:0]

wr_lane_valid[3:0]

wr_base_addr[15:0]

rd_cache_addr[15:0]

pending_lane

rd_cache_v

wr_en_r

rd_en_r

ack_r

data_in[63:0]

data_out[63:0]

error

rd_data_r[63:0]

wr_v_r

rd_v_r

err_r

SMI

SMI interface signals

SMI Interface Waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_smi16_to_reg.vhd

Horizontal Vertical

smi_addr[7:0]

smi_din[15:0]

smi_dout[15:0]

smi_oen

smi_ack

smi_cs_n_i

smi_rd_n_i

smi_wr_n_i

smi_addr_i[7:0]

smi_data_i[15:0]

smi_data_o[15:0]

smi_data_oen

smi_ack_o

Sources

interfaces/hdl/radif/src/radif_smi16_to_reg.vhd