raddsp_axis_dds Datasheet

Use Cases

AXI-Stream datapath integration where module boundaries need explicit ready/valid behavior.
Reusable FPGA DSP pipelines that need fixed-point, timing-aware implementation.
Memory-mapped control/status integration with software-visible register maps.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_axis_dds is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "generic";
    DATA_WIDTH : positive := 16;
    PHASE_WIDTH : positive := 32;
    LUT_ADDR_WIDTH : positive := 4;
    FRAME_LENGTH : natural := 0;
    MEM_INIT_FILE : string := "dsp/hdl/raddsp/mem/sine_q15_16.mem"
  );
  port (
    m_axis_tvalid : out std_logic;
    m_axis_tready : in std_logic;
    m_axis_tdata : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    m_axis_tlast : out std_logic;
    clk : in std_logic;
    rst : in std_logic;
    enable_i : in std_logic;
    phase_reset_i : in std_logic;
    phase_inc_i : in std_logic_vector(PHASE_WIDTH - 1 downto 0);
    phase_offset_i : in std_logic_vector(PHASE_WIDTH - 1 downto 0);
    wav_wr_en_i : in std_logic;
    wav_wr_addr_i : in std_logic_vector(LUT_ADDR_WIDTH - 1 downto 0);
    wav_wr_data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    phase_o : out std_logic_vector(PHASE_WIDTH - 1 downto 0);
    lut_addr_o : out std_logic_vector(LUT_ADDR_WIDTH - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_raddsp_axis_dds : entity radhdl.raddsp_axis_dds
  generic map (
    VENDOR         => "xilinx",
    DEVICE_FAMILY  => "generic",
    DATA_WIDTH     => 16,
    PHASE_WIDTH    => 32,
    LUT_ADDR_WIDTH => 4,
    FRAME_LENGTH   => 0,
    MEM_INIT_FILE  => "dsp/hdl/raddsp/mem/sine_q15_16.mem"
  )
  port map (
    m_axis_tvalid  => <m_axis_tvalid_signal>,
    m_axis_tready  => <m_axis_tready_signal>,
    m_axis_tdata   => <m_axis_tdata_signal>,
    m_axis_tlast   => <m_axis_tlast_signal>,
    clk            => <clk_signal>,
    rst            => <rst_signal>,
    enable_i       => <enable_i_signal>,
    phase_reset_i  => <phase_reset_i_signal>,
    phase_inc_i    => <phase_inc_i_signal>,
    phase_offset_i => <phase_offset_i_signal>,
    wav_wr_en_i    => <wav_wr_en_i_signal>,
    wav_wr_addr_i  => <wav_wr_addr_i_signal>,
    wav_wr_data_i  => <wav_wr_data_i_signal>,
    phase_o        => <phase_o_signal>,
    lut_addr_o     => <lut_addr_o_signal>
  );

Generics

Name	Type	Default	Description
VENDOR	string	"xilinx"	Selects the vendor-specific implementation path, usually XILINX for DSP48/XPM-backed builds or generic for portable RTL.
DEVICE_FAMILY	string	"generic"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.
DATA_WIDTH	positive	16	Sets the bit width for DATA WIDTH values carried by this module.
PHASE_WIDTH	positive	32	Sets the bit width for PHASE WIDTH values carried by this module.
LUT_ADDR_WIDTH	positive	4	Sets the bit width for LUT ADDR WIDTH values carried by this module.
FRAME_LENGTH	natural	0	Sets the transform, frame, or vector size used by the datapath.
MEM_INIT_FILE	string	"dsp/hdl/raddsp/mem/sine_q15_16.mem"	Configures MEM INIT FILE for this instance.

Ports

Name	Direction	Type	Description
m_axis_tvalid	out	std_logic	Output AXI-stream valid qualifier for the current result beat.
m_axis_tready	in	std_logic	Output AXI-stream ready input from the downstream block.
m_axis_tdata	out	std_logic_vector(DATA_WIDTH - 1 downto 0)	Output AXI-stream payload containing packed processed result lanes.
m_axis_tlast	out	std_logic	Output AXI-stream frame marker aligned with the processed result beat.
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rst	in	std_logic	Active-high synchronous reset for this clock domain.
enable_i	in	std_logic	Input enable i signal for this module.
phase_reset_i	in	std_logic	Input phase reset i signal for this module.
phase_inc_i	in	std_logic_vector(PHASE_WIDTH - 1 downto 0)	Input phase inc i signal for this module.
phase_offset_i	in	std_logic_vector(PHASE_WIDTH - 1 downto 0)	Input phase offset i signal for this module.
wav_wr_en_i	in	std_logic	Input wav wr en i signal for this module.
wav_wr_addr_i	in	std_logic_vector(LUT_ADDR_WIDTH - 1 downto 0)	Input wav wr addr i signal for this module.
wav_wr_data_i	in	std_logic_vector(DATA_WIDTH - 1 downto 0)	Input wav wr data i signal for this module.
phase_o	out	std_logic_vector(PHASE_WIDTH - 1 downto 0)	Output phase o signal generated by this module.
lut_addr_o	out	std_logic_vector(LUT_ADDR_WIDTH - 1 downto 0)	Output lut addr o signal generated by this module.

Measured Implementation Metrics

Metrics are generated by RadBuild from real Vivado synthesis reports for representative device targets. Raw report paths are preserved in the checked summary JSON.

Part	Clock ns	MHz	LUTs	FFs	BRAM tiles	DSPs	Setup WNS ns	Hold WHS ns	Generics	Summary
xc7z020clg400-1	10.0	100.0	71	38	-	0	6.518	0.158	-	projects/synth_reports/raddsp_axis_dds/xc7z020clg400-1/synth_summary.json

Register Interfaces

No fixed register map was found; this section documents the exposed register/control interface ports.

Interface	Directions	Signals	Representative ports
M_AXIS	in, out	4	m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tlast
Register control/status	in	3	wav_wr_en_i, wav_wr_addr_i, wav_wr_data_i

Testbenches

No directly associated testbench was found.

Sources

dsp/hdl/raddsp/src/raddsp_axis_dds.vhd