radif_reg_bank

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_regbank.all;

Component Declaration

component radif_reg_bank is
  generic (
    DATA_WIDTH : integer := 32;
    ADDR_WIDTH : integer := 16;
    READ_ONLY_REG_COUNT : integer := 8;
    READ_WRITE_REG_COUNT : integer := 64;
    VENDOR_TAG : string := "XILINX";
    PRODUCT_SERIES_TAG : string := "GENERIC"
  );
  port (
    clk : in std_logic;
    rstn : in std_logic;
    wr_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
    rd_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
    wr_en : in std_logic;
    rd_en : in std_logic;
    data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    read_only_regs_i : in radif_reg_array_t(0 to READ_ONLY_REG_COUNT - 1)(DATA_WIDTH - 1 downto 0);
    read_write_regs_o : out radif_reg_array_t(0 to READ_WRITE_REG_COUNT - 1)(DATA_WIDTH - 1 downto 0);
    wr_rdy : out std_logic;
    rd_rdy : out std_logic;
    wr_valid : out std_logic;
    rd_valid : out std_logic;
    error : out std_logic
  );
end component;

Direct Entity Instantiation

u_radif_reg_bank : entity radhdl.radif_reg_bank
  generic map (
    DATA_WIDTH           => 32,
    ADDR_WIDTH           => 16,
    READ_ONLY_REG_COUNT  => 8,
    READ_WRITE_REG_COUNT => 64,
    VENDOR_TAG           => "XILINX",
    PRODUCT_SERIES_TAG   => "GENERIC"
  )
  port map (
    clk               => <clk_signal>,
    rstn              => <rstn_signal>,
    wr_addr           => <wr_addr_signal>,
    rd_addr           => <rd_addr_signal>,
    wr_en             => <wr_en_signal>,
    rd_en             => <rd_en_signal>,
    data_in           => <data_in_signal>,
    data_out          => <data_out_signal>,
    read_only_regs_i  => <read_only_regs_i_signal>,
    read_write_regs_o => <read_write_regs_o_signal>,
    wr_rdy            => <wr_rdy_signal>,
    rd_rdy            => <rd_rdy_signal>,
    wr_valid          => <wr_valid_signal>,
    rd_valid          => <rd_valid_signal>,
    error             => <error_signal>
  );