raddsp_xilinx_dsp48_mul Datasheet

Use Cases

Reusable FPGA DSP pipelines that need fixed-point, timing-aware implementation.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_xilinx_dsp48_mul is
  generic (
    DEVICE_FAMILY : string := "7series";
    A_WIDTH : positive := 16;
    B_WIDTH : positive := 18
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    valid_i : in std_logic;
    subtract_i : in std_logic;
    last_i : in std_logic;
    a_i : in signed(A_WIDTH - 1 downto 0);
    b_i : in signed(B_WIDTH - 1 downto 0);
    valid_o : out std_logic;
    subtract_o : out std_logic;
    last_o : out std_logic;
    p_o : out signed(47 downto 0)
  );
end component;

Direct Entity Instantiation

u_raddsp_xilinx_dsp48_mul : entity radhdl.raddsp_xilinx_dsp48_mul
  generic map (
    DEVICE_FAMILY => "7series",
    A_WIDTH       => 16,
    B_WIDTH       => 18
  )
  port map (
    clk        => <clk_signal>,
    rst        => <rst_signal>,
    valid_i    => <valid_i_signal>,
    subtract_i => <subtract_i_signal>,
    last_i     => <last_i_signal>,
    a_i        => <a_i_signal>,
    b_i        => <b_i_signal>,
    valid_o    => <valid_o_signal>,
    subtract_o => <subtract_o_signal>,
    last_o     => <last_o_signal>,
    p_o        => <p_o_signal>
  );

Generics

Name	Type	Default	Description
DEVICE_FAMILY	string	"7series"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.
A_WIDTH	positive	16	Sets the bit width for A WIDTH values carried by this module.
B_WIDTH	positive	18	Sets the bit width for B WIDTH values carried by this module.

Ports

Name	Direction	Type	Description
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rst	in	std_logic	Active-high synchronous reset for this clock domain.
valid_i	in	std_logic	Input valid qualifier for this operation or sideband channel.
subtract_i	in	std_logic	Input subtract i signal for this module.
last_i	in	std_logic	Input last i signal for this module.
a_i	in	signed(A_WIDTH - 1 downto 0)	Input a i signal for this module.
b_i	in	signed(B_WIDTH - 1 downto 0)	Input b i signal for this module.
valid_o	out	std_logic	Output valid qualifier aligned with the produced result.
subtract_o	out	std_logic	Output subtract o signal generated by this module.
last_o	out	std_logic	Output last o signal generated by this module.
p_o	out	signed(47 downto 0)	Output p o signal generated by this module.

Testbenches

No directly associated testbench was found.

Sources

dsp/hdl/raddsp/src/raddsp_xilinx_dsp48_mul.vhd