raddsp_axis_matrix_dot

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_matrix.all;

Component Declaration

component raddsp_axis_matrix_dot is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "generic";
    DATA_WIDTH : positive := 16;
    ACC_WIDTH : positive := 48;
    COEFF_FRAC_BITS : natural := 15
  );
  port (
    s0_axis_tvalid : in std_logic;
    s0_axis_tready : out std_logic;
    s0_axis_tdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    s0_axis_tlast : in std_logic;
    s1_axis_tvalid : in std_logic;
    s1_axis_tready : out std_logic;
    s1_axis_tdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    s1_axis_tlast : in std_logic;
    m_axis_tvalid : out std_logic;
    m_axis_tready : in std_logic;
    m_axis_tdata : out std_logic_vector(ACC_WIDTH - 1 downto 0);
    m_axis_tlast : out std_logic;
    clk : in std_logic;
    rst : in std_logic;
    clear_i : in std_logic;
    sample_count_o : out std_logic_vector(31 downto 0)
  );
end component;

Direct Entity Instantiation

u_raddsp_axis_matrix_dot : entity radhdl.raddsp_axis_matrix_dot
  generic map (
    VENDOR          => "xilinx",
    DEVICE_FAMILY   => "generic",
    DATA_WIDTH      => 16,
    ACC_WIDTH       => 48,
    COEFF_FRAC_BITS => 15
  )
  port map (
    s0_axis_tvalid => <s0_axis_tvalid_signal>,
    s0_axis_tready => <s0_axis_tready_signal>,
    s0_axis_tdata  => <s0_axis_tdata_signal>,
    s0_axis_tlast  => <s0_axis_tlast_signal>,
    s1_axis_tvalid => <s1_axis_tvalid_signal>,
    s1_axis_tready => <s1_axis_tready_signal>,
    s1_axis_tdata  => <s1_axis_tdata_signal>,
    s1_axis_tlast  => <s1_axis_tlast_signal>,
    m_axis_tvalid  => <m_axis_tvalid_signal>,
    m_axis_tready  => <m_axis_tready_signal>,
    m_axis_tdata   => <m_axis_tdata_signal>,
    m_axis_tlast   => <m_axis_tlast_signal>,
    clk            => <clk_signal>,
    rst            => <rst_signal>,
    clear_i        => <clear_i_signal>,
    sample_count_o => <sample_count_o_signal>
  );