radif_spi_slave_to_reg Datasheet

Use Cases

Memory-mapped control/status integration with software-visible register maps.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_spi.all;

Component Declaration

component radif_spi_slave_to_reg is
  generic (
    DATA_WIDTH : integer := 32;
    ADDR_WIDTH : integer := 16;
    SPI_MODE : integer := 0;
    ENABLE_CRC16 : boolean := false;
    VENDOR_TAG : string := "XILINX";
    PRODUCT_SERIES_TAG : string := "GENERIC"
  );
  port (
    clk : in std_logic;
    rstn : in std_logic;
    spi_sclk_i : in std_logic;
    spi_cs_n_i : in std_logic;
    spi_mosi_i : in std_logic;
    spi_miso_o : out std_logic;
    spi_miso_oen : out std_logic;
    reg_wr_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
    reg_rd_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
    reg_wr_en : out std_logic;
    reg_rd_en : out std_logic;
    reg_data_in : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_wr_rdy : in std_logic;
    reg_rd_rdy : in std_logic;
    reg_wr_valid : in std_logic;
    reg_rd_valid : in std_logic;
    reg_error : in std_logic
  );
end component;

Direct Entity Instantiation

u_radif_spi_slave_to_reg : entity radhdl.radif_spi_slave_to_reg
  generic map (
    DATA_WIDTH         => 32,
    ADDR_WIDTH         => 16,
    SPI_MODE           => 0,
    ENABLE_CRC16       => false,
    VENDOR_TAG         => "XILINX",
    PRODUCT_SERIES_TAG => "GENERIC"
  )
  port map (
    clk          => <clk_signal>,
    rstn         => <rstn_signal>,
    spi_sclk_i   => <spi_sclk_i_signal>,
    spi_cs_n_i   => <spi_cs_n_i_signal>,
    spi_mosi_i   => <spi_mosi_i_signal>,
    spi_miso_o   => <spi_miso_o_signal>,
    spi_miso_oen => <spi_miso_oen_signal>,
    reg_wr_addr  => <reg_wr_addr_signal>,
    reg_rd_addr  => <reg_rd_addr_signal>,
    reg_wr_en    => <reg_wr_en_signal>,
    reg_rd_en    => <reg_rd_en_signal>,
    reg_data_in  => <reg_data_in_signal>,
    reg_data_out => <reg_data_out_signal>,
    reg_wr_rdy   => <reg_wr_rdy_signal>,
    reg_rd_rdy   => <reg_rd_rdy_signal>,
    reg_wr_valid => <reg_wr_valid_signal>,
    reg_rd_valid => <reg_rd_valid_signal>,
    reg_error    => <reg_error_signal>
  );

Generics

Name	Type	Default	Description
DATA_WIDTH	integer	32	Sets the bit width for DATA WIDTH values carried by this module.
ADDR_WIDTH	integer	16	Sets the bit width for ADDR WIDTH values carried by this module.
SPI_MODE	integer	0	Configures SPI MODE for this instance.
ENABLE_CRC16	boolean	false	Configures ENABLE CRC16 for this instance.
VENDOR_TAG	string	"XILINX"	Selects the vendor-specific implementation path, usually XILINX for DSP48/XPM-backed builds or generic for portable RTL.
PRODUCT_SERIES_TAG	string	"GENERIC"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.

Ports

Name	Direction	Type	Description
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rstn	in	std_logic	Active-low reset for this clock domain.
spi_sclk_i	in	std_logic	Input spi sclk i signal for this module.
spi_cs_n_i	in	std_logic	Input spi cs n i signal for this module.
spi_mosi_i	in	std_logic	Input spi mosi i signal for this module.
spi_miso_o	out	std_logic	Output spi miso o signal generated by this module.
spi_miso_oen	out	std_logic	Spi miso oen interface signal.
reg_wr_addr	out	std_logic_vector(ADDR_WIDTH - 1 downto 0)	Register write address issued to the internal RadIF register target.
reg_rd_addr	out	std_logic_vector(ADDR_WIDTH - 1 downto 0)	Register read address issued to the internal RadIF register target.
reg_wr_en	out	std_logic	One-cycle write request pulse for the internal register target.
reg_rd_en	out	std_logic	One-cycle read request pulse for the internal register target.
reg_data_in	out	std_logic_vector(DATA_WIDTH - 1 downto 0)	Write data presented to the internal register target.
reg_data_out	in	std_logic_vector(DATA_WIDTH - 1 downto 0)	Read data returned by the internal register target.
reg_wr_rdy	in	std_logic	Write-side ready indication from the internal register target.
reg_rd_rdy	in	std_logic	Read-side ready indication from the internal register target.
reg_wr_valid	in	std_logic	Write response valid indication from the internal register target.
reg_rd_valid	in	std_logic	Read response valid indication from the internal register target.
reg_error	in	std_logic	Register target error flag converted into the external bus error response.

Register Interfaces

No fixed register map was found; this section documents the exposed register/control interface ports.

Interface	Directions	Signals	Representative ports
Register control/status	in, out	11	reg_wr_addr, reg_rd_addr, reg_wr_en, reg_rd_en, reg_data_in, reg_data_out, reg_wr_rdy, reg_rd_rdy, +3 more

Testbenches

tb_radif_interfaces_smoke captured waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_interfaces_smoke.vhd

Interface elaboration and idle-state smoke testbench. This bench instantiates the RADIF SPI, QSPI, I2C, DMA, and SPI-to-AXI blocks together to catch compile/elaboration issues and verify reset-idle behavior for shared interface wrappers. It intentionally does not drive complete bus transactions; it checks that inactive SPI/QSPI pins remain tri-stated after reset. Use the module-specific testbenches for transaction waveforms.

Artifacts: status, vcd

Captured GHDL Waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_interfaces_smoke.vhd

Horizontal Vertical

clk

rstn

dma_reg_wr_addr[15:0]

dma_reg_rd_addr[15:0]

dma_reg_wr_en

dma_reg_rd_en

dma_reg_din[31:0]

dma_reg_dout[31:0]

dma_wr_rdy

dma_rd_rdy

dma_wr_valid

dma_rd_valid

dma_error

irq

awaddr[31:0]

awlen[7:0]

awsize[2:0]

awburst[1:0]

awvalid

wdata[31:0]

wstrb[3:0]

wlast

wvalid

araddr[31:0]

arlen[7:0]

arsize[2:0]

arburst[1:0]

arvalid

rready

bready

m_tdata[31:0]

m_tvalid

m_tlast

s_tready

sa_awaddr[31:0]

sa_awlen[7:0]

sa_awsize[2:0]

sa_awburst[1:0]

sa_awvalid

sa_wdata[31:0]

sa_wstrb[3:0]

sa_wlast

sa_wvalid

sa_bready

sa_araddr[31:0]

sa_arlen[7:0]

sa_arsize[2:0]

sa_arburst[1:0]

sa_arvalid

sa_rready

reg_wr_addr[15:0]

reg_rd_addr[15:0]

reg_wr_en

reg_rd_en

reg_data_in[31:0]

reg_data_out[31:0]

reg_wr_rdy

reg_rd_rdy

reg_wr_valid

reg_rd_valid

reg_error

sclk_meta

sclk_sync

sclk_prev

cs_meta

cs_sync

mosi_meta

mosi_sync

rx_shift[7:0]

tx_shift[7:0]

bit_count[2:0]

op_r[7:0]

addr_r[15:0]

wr_data_r[31:0]

wr_addr_r[15:0]

rd_addr_r[15:0]

wr_en_r

rd_en_r

data_index

tx_word[31:0]

tx_index

status_r[7:0]

io_meta[3:0]

io_sync[3:0]

nibble_high

tx_active

scl_meta

scl_sync

scl_prev

sda_meta

sda_sync

sda_prev

sda_oen_r

byte_index

selected

irq_o

I2C interface signals

I2C Interface Waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_interfaces_smoke.vhd

Horizontal Vertical

i2c_scl

i2c_sda

i2c_oen

i2c_wr_addr[15:0]

i2c_rd_addr[15:0]

i2c_wr_en

i2c_rd_en

i2c_din[31:0]

i2c_dout[31:0]

i2c_wr_valid

i2c_rd_valid

i2c_scl_i

i2c_sda_i

i2c_sda_oen

M_AXI interface signals

M_AXI Interface Waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_interfaces_smoke.vhd

Horizontal Vertical

m_axi_awaddr[31:0]

m_axi_awlen[7:0]

m_axi_awsize[2:0]

m_axi_awburst[1:0]

m_axi_awvalid

m_axi_awready

m_axi_wdata[31:0]

m_axi_wstrb[3:0]

m_axi_wlast

m_axi_wvalid

m_axi_wready

m_axi_bresp[1:0]

m_axi_bvalid

m_axi_bready

m_axi_araddr[31:0]

m_axi_arlen[7:0]

m_axi_arsize[2:0]

m_axi_arburst[1:0]

m_axi_arvalid

m_axi_arready

m_axi_rdata[31:0]

m_axi_rresp[1:0]

m_axi_rlast

m_axi_rvalid

m_axi_rready

M_AXIS interface signals

M_AXIS Interface Waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_interfaces_smoke.vhd

Horizontal Vertical

m_axis_tdata[31:0]

m_axis_tvalid

m_axis_tready

m_axis_tlast

QSPI interface signals

QSPI Interface Waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_interfaces_smoke.vhd

Horizontal Vertical

qspi_sclk

qspi_cs_n

qspi_io_i[3:0]

qspi_io_o[3:0]

qspi_oen[3:0]

qspi_wr_addr[15:0]

qspi_rd_addr[15:0]

qspi_wr_en

qspi_rd_en

qspi_din[31:0]

qspi_dout[31:0]

qspi_wr_valid

qspi_rd_valid

qspi_sclk_i

qspi_cs_n_i

qspi_io_oen[3:0]

SPI interface signals

SPI Interface Waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_interfaces_smoke.vhd

Horizontal Vertical

spi_sclk

spi_cs_n

spi_mosi

spi_miso

spi_oen

spi_wr_addr[15:0]

spi_rd_addr[15:0]

spi_wr_en

spi_rd_en

spi_din[31:0]

spi_dout[31:0]

spi_wr_valid

spi_rd_valid

spi_sclk_i

spi_cs_n_i

spi_mosi_i

spi_miso_o

spi_miso_oen

S_AXIS interface signals

S_AXIS Interface Waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_interfaces_smoke.vhd

Horizontal Vertical

s_axis_tdata[31:0]

s_axis_tvalid

s_axis_tready

s_axis_tlast

Sources

interfaces/hdl/radif/src/radif_spi_slave_to_reg.vhd