raddsp_sqrt_u32 Datasheet

Use Cases

Reusable FPGA DSP pipelines that need fixed-point, timing-aware implementation.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_sqrt_u32 is
  generic (
    INPUT_WIDTH : positive := 32;
    OUTPUT_WIDTH : positive := 16
  );
  port (
    m_axis_tvalid : out std_logic;
    m_axis_tready : in std_logic;
    s_axis_tvalid : in std_logic;
    s_axis_tready : out std_logic;
    clk : in std_logic;
    rst : in std_logic;
    x_i : in std_logic_vector(INPUT_WIDTH - 1 downto 0);
    root_o : out std_logic_vector(OUTPUT_WIDTH - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_raddsp_sqrt_u32 : entity radhdl.raddsp_sqrt_u32
  generic map (
    INPUT_WIDTH  => 32,
    OUTPUT_WIDTH => 16
  )
  port map (
    m_axis_tvalid => <m_axis_tvalid_signal>,
    m_axis_tready => <m_axis_tready_signal>,
    s_axis_tvalid => <s_axis_tvalid_signal>,
    s_axis_tready => <s_axis_tready_signal>,
    clk           => <clk_signal>,
    rst           => <rst_signal>,
    x_i           => <x_i_signal>,
    root_o        => <root_o_signal>
  );

Generics

Name	Type	Default	Description
INPUT_WIDTH	positive	32	Width of the unsigned radicand.
OUTPUT_WIDTH	positive	16	Width of the unsigned square-root result.

Ports

Name	Direction	Type	Description
m_axis_tvalid	out	std_logic	Output root valid.
m_axis_tready	in	std_logic	Output root ready.
s_axis_tvalid	in	std_logic	Input sample valid.
s_axis_tready	out	std_logic	Input sample ready. Deasserts only when output backpressure stalls the pipeline.
clk	in	std_logic	Pipeline clock.
rst	in	std_logic	Active-high synchronous reset.
x_i	in	std_logic_vector(INPUT_WIDTH - 1 downto 0)	Unsigned radicand.
root_o	out	std_logic_vector(OUTPUT_WIDTH - 1 downto 0)	Floor square-root result.

Register Interfaces

No fixed register map was found; this section documents the exposed register/control interface ports.

Interface	Directions	Signals	Representative ports
M_AXIS	in, out	2	m_axis_tvalid, m_axis_tready
S_AXIS	in, out	2	s_axis_tvalid, s_axis_tready

Testbenches

tb_raddsp_sqrt_u32 captured waveform

Source: dsp/hdl/testbenches/tb_raddsp_sqrt_u32.vhd

Verifies the pipelined raddsp_sqrt_u32 restoring square-root core. The sequence covers small exact squares, neighboring non-squares, wide 32-bit values, continuous input acceptance, and output backpressure stalls.

Artifacts: status, vcd

Data Plots

Unsigned Square-Root Sweep

Pipelined square-root output over the directed input sweep.

Captured GHDL Waveform

Source: dsp/hdl/testbenches/tb_raddsp_sqrt_u32.vhd

Horizontal Vertical

clk

rst

x_i[31:0]

root_o[15:0]

sent_count

recv_count

wr_index

rd_index

cycle_count

valid_pipe[0:16]

pipe_en

S_AXIS

M_AXIS

M_AXIS interface signals

M_AXIS Interface Waveform

Source: dsp/hdl/testbenches/tb_raddsp_sqrt_u32.vhd

Horizontal Vertical

m_axis_tvalid

m_axis_tready

S_AXIS interface signals

S_AXIS Interface Waveform

Source: dsp/hdl/testbenches/tb_raddsp_sqrt_u32.vhd

Horizontal Vertical

s_axis_tvalid

s_axis_tready

Sources

dsp/hdl/raddsp/src/raddsp_sqrt_u32.vhd