raddsp_axis_frame_stats Datasheet

Use Cases

AXI-Stream datapath integration where module boundaries need explicit ready/valid behavior.
Reusable FPGA DSP pipelines that need fixed-point, timing-aware implementation.
Memory-mapped control/status integration with software-visible register maps.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_detection.all;

Component Declaration

component raddsp_axis_frame_stats is
  generic (
    VENDOR : string := "xilinx";
    DEVICE_FAMILY : string := "generic";
    DATA_WIDTH : positive := 16;
    COUNT_WIDTH : positive := 32;
    POWER_WIDTH : positive := 64
  );
  port (
    m_axis_tvalid : out std_logic;
    m_axis_tready : in std_logic;
    m_axis_tdata : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    m_axis_tlast : out std_logic;
    s_axis_tvalid : in std_logic;
    s_axis_tready : out std_logic;
    s_axis_tdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    s_axis_tlast : in std_logic;
    clk : in std_logic;
    rst : in std_logic;
    clear_i : in std_logic;
    stats_valid_o : out std_logic;
    peak_o : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    sum_squares_o : out std_logic_vector(POWER_WIDTH - 1 downto 0);
    sample_count_o : out std_logic_vector(COUNT_WIDTH - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_raddsp_axis_frame_stats : entity radhdl.raddsp_axis_frame_stats
  generic map (
    VENDOR        => "xilinx",
    DEVICE_FAMILY => "generic",
    DATA_WIDTH    => 16,
    COUNT_WIDTH   => 32,
    POWER_WIDTH   => 64
  )
  port map (
    m_axis_tvalid  => <m_axis_tvalid_signal>,
    m_axis_tready  => <m_axis_tready_signal>,
    m_axis_tdata   => <m_axis_tdata_signal>,
    m_axis_tlast   => <m_axis_tlast_signal>,
    s_axis_tvalid  => <s_axis_tvalid_signal>,
    s_axis_tready  => <s_axis_tready_signal>,
    s_axis_tdata   => <s_axis_tdata_signal>,
    s_axis_tlast   => <s_axis_tlast_signal>,
    clk            => <clk_signal>,
    rst            => <rst_signal>,
    clear_i        => <clear_i_signal>,
    stats_valid_o  => <stats_valid_o_signal>,
    peak_o         => <peak_o_signal>,
    sum_squares_o  => <sum_squares_o_signal>,
    sample_count_o => <sample_count_o_signal>
  );

Generics

Name	Type	Default	Description
VENDOR	string	"xilinx"	Selects the vendor-specific implementation path, usually XILINX for DSP48/XPM-backed builds or generic for portable RTL.
DEVICE_FAMILY	string	"generic"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.
DATA_WIDTH	positive	16	Sets the bit width for DATA WIDTH values carried by this module.
COUNT_WIDTH	positive	32	Sets the bit width for COUNT WIDTH values carried by this module.
POWER_WIDTH	positive	64	Sets the bit width for POWER WIDTH values carried by this module.

Ports

Name	Direction	Type	Description
m_axis_tvalid	out	std_logic	Output AXI-stream valid qualifier for the current result beat.
m_axis_tready	in	std_logic	Output AXI-stream ready input from the downstream block.
m_axis_tdata	out	std_logic_vector(DATA_WIDTH - 1 downto 0)	Output AXI-stream payload containing packed processed result lanes.
m_axis_tlast	out	std_logic	Output AXI-stream frame marker aligned with the processed result beat.
s_axis_tvalid	in	std_logic	Input AXI-stream valid qualifier for the current sample beat.
s_axis_tready	out	std_logic	Input AXI-stream ready response indicating this block can accept a beat.
s_axis_tdata	in	std_logic_vector(DATA_WIDTH - 1 downto 0)	Input AXI-stream payload containing packed sample or feature lanes.
s_axis_tlast	in	std_logic	Input AXI-stream frame marker for the final beat of a frame.
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rst	in	std_logic	Active-high synchronous reset for this clock domain.
clear_i	in	std_logic	Input clear i signal for this module.
stats_valid_o	out	std_logic	Output valid qualifier aligned with the produced result.
peak_o	out	std_logic_vector(DATA_WIDTH - 1 downto 0)	Output peak o signal generated by this module.
sum_squares_o	out	std_logic_vector(POWER_WIDTH - 1 downto 0)	Output sum squares o signal generated by this module.
sample_count_o	out	std_logic_vector(COUNT_WIDTH - 1 downto 0)	Output sample vector or current sample status from the datapath.

Register Interfaces

No fixed register map was found; this section documents the exposed register/control interface ports.

Interface	Directions	Signals	Representative ports
M_AXIS	in, out	4	m_axis_tvalid, m_axis_tready, m_axis_tdata, m_axis_tlast
S_AXIS	in, out	4	s_axis_tvalid, s_axis_tready, s_axis_tdata, s_axis_tlast

Testbenches

No directly associated testbench was found.

Sources

dsp/hdl/raddsp/src/raddsp_axis_frame_stats.vhd