Radical Computer Technologies
RadHDL Documentation

Getting Started

Documentation version: 0.2.2-beta.1

RadHDL is a VHDL-first FPGA library for portable interfaces, DSP blocks, debug cores, and explicit vendor primitive wrappers.

RadHDL Overview

RadHDL is organized around reusable packages instead of board-local one-off HDL. The current Crimson beta line includes RADIF interface blocks, RADDSP signal-processing blocks, RadDebug/RadILA observability blocks, and RadPrimitive wrappers for RAM, FIFO, CDC, and DSP resources.

The RadPrimitive layer is intentionally explicit. Portable top-level designs instantiate a vendor-neutral wrapper such as radhdl_ram or radhdl_fifo, while the lower-level implementation selects Xilinx, Lattice, Gowin, or generic simulation models through configuration. Primitive-backed synthesis paths should use real vendor primitives rather than silent inference.

Install With RadBuild

sudo apt update
sudo apt install radbuild radbuild-radhdl radbuild-doc

radbuild-hdlgen --help
radhdl-docgen build --radhdl /usr/share/radbuild/radhdl --out ./radhdl-docs

The radbuild-radhdl package installs the current HDL catalog under /usr/share/radbuild/radhdl. RadBuild projects can reference packaged HDL directly, or point at a local RadHDL checkout while developing library changes.

Use With Vendor Toolchains

RadHDL source can also be used directly in vendor projects. Add the package VHDL files for the blocks you instantiate, then include project-specific constraints and build scripts. For Xilinx, keep XPM use isolated inside RadPrimitive wrappers. For Gowin and Lattice, prefer the matching explicit primitive wrappers or the provided generic simulation models when validating behavior with GHDL.

Package Structure

common/hdl/srcRadPrimitive public wrappers and common primitive infrastructure.
interfaces/hdl/radifRegister banks, AXI/AXIS bridges, I2C, I2S, SPI, UART, and simple management interfaces.
dsp/hdl/raddspDSP transforms, filters, detection blocks, audio synthesis, and vendor DSP wrappers.
debug/radilaPortable ILA and RadDebugHub capture infrastructure.
projects/examplesIntegration examples such as the FPiGA Audio Hat shared-math design.
scriptsDocumentation generation, simulation matrix, and helper tooling.

Example Workflow

  1. Choose a portable interface such as radif_reg_bank or radif_i2s_axis.
  2. Open the module datasheet from the searchable catalog and copy the instantiation template.
  3. Run the relevant GHDL testbench before integrating it into a board-level project.
  4. For vendor primitives, run the primitive simulation matrix so generic and vendor-specific behavior stay aligned.
  5. Commit source HDL, constraints, and RadBuild JSON project files; keep generated vendor build outputs out of revision control.

Guides

radif_reg_bank Datasheet radhdl_ram Datasheet RadDebugHub Datasheet Version Change Notes