Highlights
- Expanded RadPrimitive coverage for vendor-neutral RAM, FIFO, CDC, and DSP wrapper entry points.
- Added explicit Gowin and Lattice primitive-backed paths where available, while keeping generic models available for simulation and unsupported families.
- Added searchable datasheet organization for primitive RAM, FIFO, CDC, DSP, RADIF interface, RADDSP, and RadDebug/RadILA modules.
- Added contribution guidance for primitive policy, simulation expectations, and HDL style.
- Packaged the FPiGA Audio Hat shared-math example with top-level I2C/I2S simulation infrastructure.
- Refreshed RadBuild integration so the packaged RadHDL catalog can be consumed by beta RadBuild projects.
Datasheet Coverage
| Datasheets | 98 generated module datasheets |
|---|---|
| Testbenches | 29 indexed testbenches |
| Register maps | 16 indexed register maps |
| Primitive datasheets | RAM, FIFO, CDC, and DSP primitive groups are separately searchable. |
Known Follow-Up
The next hardening pass should continue expanding primitive simulation matrix coverage, add more vendor-authoritative simulation comparisons, and publish board bring-up evidence for the FPiGA Audio Hat path.