Designing With radif_reg_bank

Where It Fits

radif_reg_bank provides synchronous read/write storage for software-visible registers. Read-write registers are stored internally and exported to your logic. Read-only registers are supplied by your logic and appear after the read-write range in the same byte-addressed register space.

Host bridge
  AXI-Lite, SPI, UART, SMI, or I2C
        |
        v
RadIF register transaction signals
        |
        v
radif_reg_bank
        |
        +-- read_write_regs_o: control values into your logic
        +-- read_only_regs_i:  status values from your logic

Minimal Instance

The current entity exposes simple address, read, write, data, ready, valid, and error signals. Addresses are byte addresses; for a 32-bit register bank, offsets advance by four bytes.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.radif_pkg.all;

signal ro_regs : radif_reg_array_t(0 to 1)(31 downto 0);
signal rw_regs : radif_reg_array_t(0 to 7)(31 downto 0);

u_regs : entity work.radif_reg_bank
  generic map (
    DATA_WIDTH           => 32,
    ADDR_WIDTH           => 16,
    READ_ONLY_REG_COUNT  => 2,
    READ_WRITE_REG_COUNT => 8,
    VENDOR_TAG           => "GENERIC",
    PRODUCT_SERIES_TAG   => "GENERIC"
  )
  port map (
    clk               => clk,
    rstn              => rstn,
    wr_addr           => reg_wr_addr,
    rd_addr           => reg_rd_addr,
    wr_en             => reg_wr_en,
    rd_en             => reg_rd_en,
    data_in           => reg_wdata,
    data_out          => reg_rdata,
    read_only_regs_i  => ro_regs,
    read_write_regs_o => rw_regs,
    wr_rdy            => reg_wr_rdy,
    rd_rdy            => reg_rd_rdy,
    wr_valid          => reg_wr_valid,
    rd_valid          => reg_rd_valid,
    error             => reg_error
  );

Register Layout

Design Checklist

• Compile radif_pkg before compiling radif_reg_bank.
• Keep READ_ONLY_REG_COUNT and READ_WRITE_REG_COUNT greater than zero.
• Define a register map in source control so firmware and host software use stable offsets.
• Use radif_reg_interconnect when one host bridge must route to multiple register blocks.
• Use vendor tags consistently so future primitive-backed variants can be selected without changing application-level VHDL.

Next Steps

After the bank is working in simulation, connect it to a host bridge such as radif_axi_lite_to_reg, radif_uart_to_reg, or radif_reg_to_spi_master. For larger designs, split control/status into multiple banks and route them with radif_reg_interconnect.