Radical Computer Technologies

RadHDL Documentation

RadHDL 0.2.2 Documentation

Documentation version: 0.2.2-beta.1 / Experimental Crimson release

RadHDL 0.2.2 documents the portable VHDL library, the new RadPrimitive vendor abstraction layer, package structure, RadBuild and standalone toolchain workflows, and the generated module datasheets.

Start Here

Getting StartedOverview, installation, RadBuild use, standalone vendor-toolchain use, package structure, and guide links. Version Change Notes0.2.2-beta.1 highlights, validation status, generator fix notes, and known documentation gaps. GuidesWorkflow examples, starting with a software-visible register block based on radif_reg_bank. Type ReferencePackage-level records, constants, subtypes, and helper functions.

0.2.2 Highlights

RadPrimitive DatasheetsThe searchable datasheet browser now includes 24 primitive datasheets for RAM, FIFO, CDC, Xilinx, Lattice, Gowin, and ECP5 wrapper boundaries.

Primitive Simulation MatrixGHDL is the default open simulator for portable models; Vivado xsim is used where XPM SystemVerilog bodies are authoritative.

Board DirectionThe release prepares Xilinx 7 Series, UltraScale, UltraScale+, Lattice ECP5, and Gowin GW5A targets for a common VHDL source flow.

RadBuild ReadinessThe docs describe consuming RadHDL through RadBuild packages or directly from vendor project scripts.

Catalog Summary

Version	0.2.2
Datasheets	98
Testbenches	29
Register maps	16
Type packages	9

Type Reference

Package-level records, constants, subtypes, and helper functions are documented separately from module datasheets.

Open type reference

Datasheets

radprimitive 24 datasheets

primitive_ram 6 datasheets

radhdl_ecp5_dp16kd_18x1024Primitives / 10 ports / 0 generics

radhdl_lattice_ramPrimitives / 12 ports / 4 generics

radhdl_lattice_tdp_ramPrimitives / 10 ports / 4 generics

radhdl_ramPrimitives / 12 ports / 11 generics

radhdl_sample_ramPrimitives / 6 ports / 5 generics

radhdl_xilinx_ramPrimitives / 12 ports / 7 generics

primitive_fifo 10 datasheets

radhdl_fifoPrimitives / 26 ports / 21 generics

radhdl_fifo_asyncPrimitives / 14 ports / 9 generics

radhdl_fifo_bram_asyncPrimitives / 12 ports / 7 generics

radhdl_fifo_bram_syncPrimitives / 10 ports / 6 generics

radhdl_fifo_syncPrimitives / 25 ports / 19 generics

radhdl_gowin_fifo_hs_asyncPrimitives / 14 ports / 4 generics

radhdl_gowin_fifo_sc_syncPrimitives / 12 ports / 2 generics

radhdl_lattice_fifo8kbPrimitives / 12 ports / 1 generics

radhdl_xilinx_fifo_asyncPrimitives / 10 ports / 5 generics

radhdl_xilinx_fifo_syncPrimitives / 9 ports / 5 generics

primitive_cdc 7 datasheets

rad_cdc_array_singlePrimitives / 3 ports / 4 generics

rad_cdc_async_rstPrimitives / 3 ports / 3 generics

rad_cdc_grayPrimitives / 3 ports / 3 generics

rad_cdc_handshakePrimitives / 10 ports / 3 generics

rad_cdc_pulsePrimitives / 6 ports / 2 generics

rad_cdc_singlePrimitives / 3 ports / 3 generics

rad_cdc_sync_rstPrimitives / 3 ports / 3 generics

primitive_dsp 1 datasheets

radhdl_ecp5_mult18x18dPrimitives / 6 ports / 0 generics

raddsp 55 datasheets

dsp_comms 2 datasheets

raddsp_axis_am_iq_demodulatorDSP / 21 ports / 10 generics / 6 registers

raddsp_axis_am_iq_modulatorDSP / 23 ports / 10 generics / 6 registers

dsp_transform 39 datasheets

cordic_atan2DSP / 9 ports / 3 generics

fft_radix2_batch_coreDSP / 17 ports / 10 generics

fft_tdp_ramDSP / 9 ports / 6 generics

raddsp_audio_dds_oscillatorDSP / 8 ports / 5 generics

raddsp_audio_poly_synthDSP / 18 ports / 8 generics

raddsp_audio_quad_lfo_wavetableDSP / 22 ports / 6 generics

raddsp_audio_quad_osc_pan_mixerDSP / 12 ports / 3 generics

raddsp_audio_quad_wavetable_oscillatorDSP / 22 ports / 6 generics

raddsp_audio_stereo_balance_tdmDSP / 10 ports / 3 generics

raddsp_audio_stereo_gainDSP / 11 ports / 3 generics

raddsp_axis_ddsDSP / 15 ports / 7 generics

raddsp_axis_fft_bin_productDSP / 15 ports / 5 generics

raddsp_axis_fixed_to_floatDSP / 10 ports / 5 generics

raddsp_axis_float_to_fixedDSP / 10 ports / 5 generics

raddsp_axis_gainDSP / 11 ports / 6 generics

raddsp_axis_iq_magnitude_sqDSP / 10 ports / 4 generics

raddsp_axis_mix2DSP / 14 ports / 3 generics

raddsp_axis_radfftDSP / 16 ports / 18 generics

raddsp_axis_radfft_batchDSP / 15 ports / 11 generics

raddsp_axis_radfft_ddrDSP / 55 ports / 23 generics / 26 registers

raddsp_axis_radfft_iterativeDSP / 15 ports / 13 generics

raddsp_axis_radfft_parallel8DSP / 20 ports / 10 generics

raddsp_axis_radfft_radix2_tdpDSP / 20 ports / 14 generics

raddsp_axis_radfft_radix4_tdpDSP / 15 ports / 14 generics

raddsp_axis_radfft_streamingDSP / 15 ports / 14 generics

raddsp_cordic_atan2DSP / 9 ports / 3 generics

raddsp_fft_radix2_batch_coreDSP / 16 ports / 10 generics

raddsp_fft_twiddle_romDSP / 5 ports / 7 generics

raddsp_gowin_dpb16DSP / 9 ports / 1 generics

raddsp_gowin_multalu27x18_mulDSP / 6 ports / 0 generics

raddsp_gowin_multalu27x32_mulDSP / 6 ports / 0 generics

raddsp_lattice_mulDSP / 11 ports / 4 generics

raddsp_mulDSP / 11 ports / 5 generics

raddsp_sqrt_u32DSP / 8 ports / 2 generics

raddsp_square_seqDSP / 7 ports / 3 generics

raddsp_wide_mulDSP / 7 ports / 6 generics

raddsp_xilinx_dsp48_mulDSP / 11 ports / 3 generics

raddsp_xilinx_dsp48_square_seqDSP / 7 ports / 2 generics

raddsp_xilinx_dsp48_wide_mulDSP / 7 ports / 5 generics

dsp_matrix 2 datasheets

raddsp_axis_matrix_dotDSP / 16 ports / 5 generics

raddsp_axis_matrix_elementwiseDSP / 15 ports / 4 generics

dsp_filter 5 datasheets

raddsp_audio_stereo_biquad_eq_tdmDSP / 16 ports / 3 generics

raddsp_audio_stereo_shared_pg_eq_tdmDSP / 18 ports / 3 generics

raddsp_axis_biquadDSP / 16 ports / 7 generics

raddsp_axis_firDSP / 12 ports / 8 generics

raddsp_axis_one_pole_lowpassDSP / 12 ports / 6 generics

dsp_detection 7 datasheets

raddsp_axis_fft_fingerprintDSP / 29 ports / 8 generics / 16 registers

raddsp_axis_fingerprint_matcherDSP / 30 ports / 8 generics / 15 registers

raddsp_axis_frame_statsDSP / 15 ports / 5 generics

raddsp_zc_chirp_frame_detectorDSP / 17 ports / 6 generics

zc_chirp_frame_detectorDSP / 17 ports / 8 generics

zc_cross_correlatorDSP / 12 ports / 5 generics

zc_peak_detectorDSP / 13 ports / 6 generics

radif 16 datasheets

radif_axi 2 datasheets

radif_axi4_axis_dmaInterfaces / 47 ports / 12 generics / 14 registers

radif_axi_lite_to_regInterfaces / 32 ports / 5 generics

radif_i2c 3 datasheets

radif_i2c_byte_slaveInterfaces / 12 ports / 1 generics

radif_i2c_slave_to_regInterfaces / 16 ports / 6 generics

radif_reg_to_i2c_masterInterfaces / 17 ports / 5 generics / 6 registers

radif_i2s 1 datasheets

radif_i2s_axisInterfaces / 33 ports / 14 generics / 7 registers

radif_spi 4 datasheets

radif_qspi_slave_to_regInterfaces / 18 ports / 6 generics

radif_reg_to_spi_masterInterfaces / 17 ports / 6 generics / 6 registers

radif_spi_axi_masterInterfaces / 32 ports / 6 generics

radif_spi_slave_to_regInterfaces / 18 ports / 6 generics

radif_smi 1 datasheets

radif_smi16_to_regInterfaces / 21 ports / 5 generics

radif_uart 1 datasheets

radif_uart_to_regInterfaces / 15 ports / 5 generics / 2 registers

radif_regbank 4 datasheets

radif_gpio_reg_blockInterfaces / 17 ports / 7 generics / 7 registers

radif_irq_controllerInterfaces / 16 ports / 5 generics / 6 registers

radif_reg_bankInterfaces / 15 ports / 6 generics

radif_reg_interconnectInterfaces / 24 ports / 7 generics

raddebug 3 datasheets

radila 3 datasheets

RadDebugHubDebug / 18 ports / 9 generics / 16 registers

RadILADebug / 18 ports / 7 generics

radila_gowin_dpb_ramDebug / 9 ports / 2 generics