radhdl Types

type axi4_128_a64_intf_t is record aw : axi_aw64_t; w : axi_w128_t; b : axi_b_t; ar : axi_ar64_t; r : axi_r128_t; end record;

type axi4_32_a32_intf_t is record aw : axi_aw32_t; w : axi_w32_t; b : axi_b_t; ar : axi_ar32_t; r : axi_r32_t; end record;

type axi4_64_a32_intf_t is record aw : axi_aw32_t; w : axi_w64_t; b : axi_b_t; ar : axi_ar32_t; r : axi_r64_t; end record;

type axi4_64_a64_intf_t is record aw : axi_aw64_t; w : axi_w64_t; b : axi_b_t; ar : axi_ar64_t; r : axi_r64_t; end record;

type axi_ar32_t is record addr : std_logic_vector(31 downto 0); len : axi_len_t; size : axi_size_t; burst : axi_burst_t; prot : axi_prot_t; valid : std_logic; ready : std_logic; end record;

type axi_ar64_t is record addr : std_logic_vector(63 downto 0); len : axi_len_t; size : axi_size_t; burst : axi_burst_t; prot : axi_prot_t; valid : std_logic; ready : std_logic; end record;

type axi_aw32_t is record addr : std_logic_vector(31 downto 0); len : axi_len_t; size : axi_size_t; burst : axi_burst_t; prot : axi_prot_t; valid : std_logic; ready : std_logic; end record;

type axi_aw64_t is record addr : std_logic_vector(63 downto 0); len : axi_len_t; size : axi_size_t; burst : axi_burst_t; prot : axi_prot_t; valid : std_logic; ready : std_logic; end record;

type axi_b_t is record resp : axi_resp_t; valid : std_logic; ready : std_logic; end record;

type axi_r128_t is record data : std_logic_vector(127 downto 0); resp : axi_resp_t; last : std_logic; valid : std_logic; ready : std_logic; end record;

type axi_r32_t is record data : std_logic_vector(31 downto 0); resp : axi_resp_t; last : std_logic; valid : std_logic; ready : std_logic; end record;

type axi_r64_t is record data : std_logic_vector(63 downto 0); resp : axi_resp_t; last : std_logic; valid : std_logic; ready : std_logic; end record;

type axi_w128_t is record data : std_logic_vector(127 downto 0); strb : std_logic_vector(15 downto 0); last : std_logic; valid : std_logic; ready : std_logic; end record;

type axi_w32_t is record data : std_logic_vector(31 downto 0); strb : std_logic_vector(3 downto 0); last : std_logic; valid : std_logic; ready : std_logic; end record;

type axi_w64_t is record data : std_logic_vector(63 downto 0); strb : std_logic_vector(7 downto 0); last : std_logic; valid : std_logic; ready : std_logic; end record;

type axilite128_a64_intf_t is record aw : axilite_aw64_t; w : axi_w128_t; b : axi_b_t; ar : axilite_ar64_t; r : axilite_r128_t; end record;

type axilite32_a16_intf_t is record aw : axilite_aw16_t; w : axi_w32_t; b : axi_b_t; ar : axilite_ar16_t; r : axilite_r32_t; end record;

type axilite32_a32_intf_t is record aw : axilite_aw32_t; w : axi_w32_t; b : axi_b_t; ar : axilite_ar32_t; r : axilite_r32_t; end record;

type axilite64_a32_intf_t is record aw : axilite_aw32_t; w : axi_w64_t; b : axi_b_t; ar : axilite_ar32_t; r : axilite_r64_t; end record;

type axilite64_a64_intf_t is record aw : axilite_aw64_t; w : axi_w64_t; b : axi_b_t; ar : axilite_ar64_t; r : axilite_r64_t; end record;

type axilite_ar16_t is record addr : std_logic_vector(15 downto 0); prot : axi_prot_t; valid : std_logic; ready : std_logic; end record;

type axilite_ar32_t is record addr : std_logic_vector(31 downto 0); prot : axi_prot_t; valid : std_logic; ready : std_logic; end record;

type axilite_ar64_t is record addr : std_logic_vector(63 downto 0); prot : axi_prot_t; valid : std_logic; ready : std_logic; end record;

type axilite_aw16_t is record addr : std_logic_vector(15 downto 0); prot : axi_prot_t; valid : std_logic; ready : std_logic; end record;

type axilite_aw32_t is record addr : std_logic_vector(31 downto 0); prot : axi_prot_t; valid : std_logic; ready : std_logic; end record;

type axilite_aw64_t is record addr : std_logic_vector(63 downto 0); prot : axi_prot_t; valid : std_logic; ready : std_logic; end record;

type axilite_r128_t is record data : std_logic_vector(127 downto 0); resp : axi_resp_t; valid : std_logic; ready : std_logic; end record;

type axilite_r32_t is record data : std_logic_vector(31 downto 0); resp : axi_resp_t; valid : std_logic; ready : std_logic; end record;

type axilite_r64_t is record data : std_logic_vector(63 downto 0); resp : axi_resp_t; valid : std_logic; ready : std_logic; end record;

subtype axi4_128_a64_master_i_t is axi4_128_a64_intf_t;

subtype axi4_128_a64_master_o_t is axi4_128_a64_intf_t;

subtype axi4_32_a32_master_i_t is axi4_32_a32_intf_t;

subtype axi4_32_a32_master_o_t is axi4_32_a32_intf_t;

subtype axi4_64_a32_master_i_t is axi4_64_a32_intf_t;

subtype axi4_64_a32_master_o_t is axi4_64_a32_intf_t;

subtype axi4_64_a64_master_i_t is axi4_64_a64_intf_t;

subtype axi4_64_a64_master_o_t is axi4_64_a64_intf_t;

subtype axi_burst_t is std_logic_vector(1 downto 0);

subtype axi_len_t is std_logic_vector(7 downto 0);

subtype axi_prot_t is std_logic_vector(2 downto 0);

subtype axi_resp_t is std_logic_vector(1 downto 0);

subtype axi_size_t is std_logic_vector(2 downto 0);

subtype axilite128_a64_slave_i_t is axilite128_a64_intf_t;

subtype axilite128_a64_slave_o_t is axilite128_a64_intf_t;

subtype axilite32_a16_slave_i_t is axilite32_a16_intf_t;

subtype axilite32_a16_slave_o_t is axilite32_a16_intf_t;

subtype axilite32_a32_slave_i_t is axilite32_a32_intf_t;

subtype axilite32_a32_slave_o_t is axilite32_a32_intf_t;

subtype axilite64_a32_slave_i_t is axilite64_a32_intf_t;

subtype axilite64_a32_slave_o_t is axilite64_a32_intf_t;

subtype axilite64_a64_slave_i_t is axilite64_a64_intf_t;

subtype axilite64_a64_slave_o_t is axilite64_a64_intf_t;

constant AXI4_128_A64_INTF_NULL : axi4_128_a64_intf_t := (aw => AXI_AW64_NULL, w => AXI_W128_NULL, b => AXI_B_NULL, ar => AXI_AR64_NULL, r => AXI_R128_NULL);

constant AXI4_128_A64_MASTER_I_NULL : axi4_128_a64_master_i_t := AXI4_128_A64_INTF_NULL;

constant AXI4_128_A64_MASTER_O_NULL : axi4_128_a64_master_o_t := AXI4_128_A64_INTF_NULL;

constant AXI4_32_A32_INTF_NULL : axi4_32_a32_intf_t := (aw => AXI_AW32_NULL, w => AXI_W32_NULL, b => AXI_B_NULL, ar => AXI_AR32_NULL, r => AXI_R32_NULL);

constant AXI4_32_A32_MASTER_I_NULL : axi4_32_a32_master_i_t := AXI4_32_A32_INTF_NULL;

constant AXI4_32_A32_MASTER_O_NULL : axi4_32_a32_master_o_t := AXI4_32_A32_INTF_NULL;

constant AXI4_64_A32_INTF_NULL : axi4_64_a32_intf_t := (aw => AXI_AW32_NULL, w => AXI_W64_NULL, b => AXI_B_NULL, ar => AXI_AR32_NULL, r => AXI_R64_NULL);

constant AXI4_64_A32_MASTER_I_NULL : axi4_64_a32_master_i_t := AXI4_64_A32_INTF_NULL;

constant AXI4_64_A32_MASTER_O_NULL : axi4_64_a32_master_o_t := AXI4_64_A32_INTF_NULL;

constant AXI4_64_A64_INTF_NULL : axi4_64_a64_intf_t := (aw => AXI_AW64_NULL, w => AXI_W64_NULL, b => AXI_B_NULL, ar => AXI_AR64_NULL, r => AXI_R64_NULL);

constant AXI4_64_A64_MASTER_I_NULL : axi4_64_a64_master_i_t := AXI4_64_A64_INTF_NULL;

constant AXI4_64_A64_MASTER_O_NULL : axi4_64_a64_master_o_t := AXI4_64_A64_INTF_NULL;

constant AXI_AR32_NULL : axi_ar32_t := (addr => (others => '0'), len => (others => '0'), size => (others => '0'), burst => (others => '0'), prot => (others => '0'), valid => '0', ready => '0');

constant AXI_AR64_NULL : axi_ar64_t := (addr => (others => '0'), len => (others => '0'), size => (others => '0'), burst => (others => '0'), prot => (others => '0'), valid => '0', ready => '0');

constant AXI_AW32_NULL : axi_aw32_t := (addr => (others => '0'), len => (others => '0'), size => (others => '0'), burst => (others => '0'), prot => (others => '0'), valid => '0', ready => '0');

constant AXI_AW64_NULL : axi_aw64_t := (addr => (others => '0'), len => (others => '0'), size => (others => '0'), burst => (others => '0'), prot => (others => '0'), valid => '0', ready => '0');

constant AXI_B_NULL : axi_b_t := (resp => AXI_RESP_OKAY, valid => '0', ready => '0');

constant AXI_BURST_FIXED : axi_burst_t := "00";

constant AXI_BURST_INCR : axi_burst_t := "01";

constant AXI_BURST_WRAP : axi_burst_t := "10";

constant AXI_R128_NULL : axi_r128_t := (data => (others => '0'), resp => AXI_RESP_OKAY, last => '0', valid => '0', ready => '0');

constant AXI_R32_NULL : axi_r32_t := (data => (others => '0'), resp => AXI_RESP_OKAY, last => '0', valid => '0', ready => '0');

constant AXI_R64_NULL : axi_r64_t := (data => (others => '0'), resp => AXI_RESP_OKAY, last => '0', valid => '0', ready => '0');

constant AXI_RESP_DECERR : axi_resp_t := "11";

constant AXI_RESP_EXOKAY : axi_resp_t := "01";

constant AXI_RESP_OKAY : axi_resp_t := "00";

constant AXI_RESP_SLVERR : axi_resp_t := "10";

constant AXI_W128_NULL : axi_w128_t := (data => (others => '0'), strb => (others => '0'), last => '0', valid => '0', ready => '0');

constant AXI_W32_NULL : axi_w32_t := (data => (others => '0'), strb => (others => '0'), last => '0', valid => '0', ready => '0');

constant AXI_W64_NULL : axi_w64_t := (data => (others => '0'), strb => (others => '0'), last => '0', valid => '0', ready => '0');

constant AXILITE128_A64_INTF_NULL : axilite128_a64_intf_t := (aw => AXILITE_AW64_NULL, w => AXI_W128_NULL, b => AXI_B_NULL, ar => AXILITE_AR64_NULL, r => AXILITE_R128_NULL);

constant AXILITE128_A64_SLAVE_I_NULL : axilite128_a64_slave_i_t := AXILITE128_A64_INTF_NULL;

constant AXILITE128_A64_SLAVE_O_NULL : axilite128_a64_slave_o_t := AXILITE128_A64_INTF_NULL;

constant AXILITE32_A16_INTF_NULL : axilite32_a16_intf_t := (aw => AXILITE_AW16_NULL, w => AXI_W32_NULL, b => AXI_B_NULL, ar => AXILITE_AR16_NULL, r => AXILITE_R32_NULL);

constant AXILITE32_A16_SLAVE_I_NULL : axilite32_a16_slave_i_t := AXILITE32_A16_INTF_NULL;

constant AXILITE32_A16_SLAVE_O_NULL : axilite32_a16_slave_o_t := AXILITE32_A16_INTF_NULL;

constant AXILITE32_A32_INTF_NULL : axilite32_a32_intf_t := (aw => AXILITE_AW32_NULL, w => AXI_W32_NULL, b => AXI_B_NULL, ar => AXILITE_AR32_NULL, r => AXILITE_R32_NULL);

constant AXILITE32_A32_SLAVE_I_NULL : axilite32_a32_slave_i_t := AXILITE32_A32_INTF_NULL;

constant AXILITE32_A32_SLAVE_O_NULL : axilite32_a32_slave_o_t := AXILITE32_A32_INTF_NULL;

constant AXILITE64_A32_INTF_NULL : axilite64_a32_intf_t := (aw => AXILITE_AW32_NULL, w => AXI_W64_NULL, b => AXI_B_NULL, ar => AXILITE_AR32_NULL, r => AXILITE_R64_NULL);

constant AXILITE64_A32_SLAVE_I_NULL : axilite64_a32_slave_i_t := AXILITE64_A32_INTF_NULL;

constant AXILITE64_A32_SLAVE_O_NULL : axilite64_a32_slave_o_t := AXILITE64_A32_INTF_NULL;

constant AXILITE64_A64_INTF_NULL : axilite64_a64_intf_t := (aw => AXILITE_AW64_NULL, w => AXI_W64_NULL, b => AXI_B_NULL, ar => AXILITE_AR64_NULL, r => AXILITE_R64_NULL);

constant AXILITE64_A64_SLAVE_I_NULL : axilite64_a64_slave_i_t := AXILITE64_A64_INTF_NULL;

constant AXILITE64_A64_SLAVE_O_NULL : axilite64_a64_slave_o_t := AXILITE64_A64_INTF_NULL;

constant AXILITE_AR16_NULL : axilite_ar16_t := (addr => (others => '0'), prot => (others => '0'), valid => '0', ready => '0');

constant AXILITE_AR32_NULL : axilite_ar32_t := (addr => (others => '0'), prot => (others => '0'), valid => '0', ready => '0');

constant AXILITE_AR64_NULL : axilite_ar64_t := (addr => (others => '0'), prot => (others => '0'), valid => '0', ready => '0');

constant AXILITE_AW16_NULL : axilite_aw16_t := (addr => (others => '0'), prot => (others => '0'), valid => '0', ready => '0');

constant AXILITE_AW32_NULL : axilite_aw32_t := (addr => (others => '0'), prot => (others => '0'), valid => '0', ready => '0');

constant AXILITE_AW64_NULL : axilite_aw64_t := (addr => (others => '0'), prot => (others => '0'), valid => '0', ready => '0');

constant AXILITE_R128_NULL : axilite_r128_t := (data => (others => '0'), resp => AXI_RESP_OKAY, valid => '0', ready => '0');

constant AXILITE_R32_NULL : axilite_r32_t := (data => (others => '0'), resp => AXI_RESP_OKAY, valid => '0', ready => '0');

constant AXILITE_R64_NULL : axilite_r64_t := (data => (others => '0'), resp => AXI_RESP_OKAY, valid => '0', ready => '0');

function axi4_32_a32_intf(awaddr : std_logic_vector(31 downto 0); awvalid : std_logic; awready : std_logic; wdata : std_logic_vector(31 downto 0); wstrb : std_logic_vector(3 downto 0); wlast : std_logic; wvalid : std_logic; wready : std_logic; bresp : axi_resp_t; bvalid : std_logic; bready : std_logic; araddr : std_logic_vector(31 downto 0); arvalid : std_logic; arready : std_logic; rdata : std_logic_vector(31 downto 0); rresp : axi_resp_t; rlast : std_logic; rvalid : std_logic; rready : std_logic) return axi4_32_a32_intf_t;

function axi_size_from_bytes(byte_count : positive) return axi_size_t;

function axilite32_a32_intf(awaddr : std_logic_vector(31 downto 0); awvalid : std_logic; awready : std_logic; wdata : std_logic_vector(31 downto 0); wstrb : std_logic_vector(3 downto 0); wvalid : std_logic; wready : std_logic; bresp : axi_resp_t; bvalid : std_logic; bready : std_logic; araddr : std_logic_vector(31 downto 0); arvalid : std_logic; arready : std_logic; rdata : std_logic_vector(31 downto 0); rresp : axi_resp_t; rvalid : std_logic; rready : std_logic) return axilite32_a32_intf_t;

type axis128_intf_t is record aclk : std_logic; aresetn : std_logic; tvalid : std_logic; tready : std_logic; tdata : std_logic_vector(127 downto 0); tlast : std_logic; end record;

type axis128_maxis_o_t is record tvalid : std_logic; tdata : std_logic_vector(127 downto 0); tlast : std_logic; end record;

type axis128_saxis_i_t is record tvalid : std_logic; tdata : std_logic_vector(127 downto 0); tlast : std_logic; end record;

type axis16_intf_t is record aclk : std_logic; aresetn : std_logic; tvalid : std_logic; tready : std_logic; tdata : std_logic_vector(15 downto 0); tlast : std_logic; end record;

type axis16_maxis_o_t is record tvalid : std_logic; tdata : std_logic_vector(15 downto 0); tlast : std_logic; end record;

type axis16_saxis_i_t is record tvalid : std_logic; tdata : std_logic_vector(15 downto 0); tlast : std_logic; end record;

type axis32_intf_t is record aclk : std_logic; aresetn : std_logic; tvalid : std_logic; tready : std_logic; tdata : std_logic_vector(31 downto 0); tlast : std_logic; end record;

type axis32_maxis_o_t is record tvalid : std_logic; tdata : std_logic_vector(31 downto 0); tlast : std_logic; end record;

type axis32_saxis_i_t is record tvalid : std_logic; tdata : std_logic_vector(31 downto 0); tlast : std_logic; end record;

type axis64_intf_t is record aclk : std_logic; aresetn : std_logic; tvalid : std_logic; tready : std_logic; tdata : std_logic_vector(63 downto 0); tlast : std_logic; end record;

type axis64_maxis_o_t is record tvalid : std_logic; tdata : std_logic_vector(63 downto 0); tlast : std_logic; end record;

type axis64_saxis_i_t is record tvalid : std_logic; tdata : std_logic_vector(63 downto 0); tlast : std_logic; end record;

type axis8_intf_t is record aclk : std_logic; aresetn : std_logic; tvalid : std_logic; tready : std_logic; tdata : std_logic_vector(7 downto 0); tlast : std_logic; end record;

type axis8_maxis_o_t is record tvalid : std_logic; tdata : std_logic_vector(7 downto 0); tlast : std_logic; end record;

type axis8_saxis_i_t is record tvalid : std_logic; tdata : std_logic_vector(7 downto 0); tlast : std_logic; end record;

type axis_maxis_i_t is record tready : std_logic; end record;

type axis_saxis_o_t is record tready : std_logic; end record;

subtype axis128_maxis_i_t is axis_maxis_i_t;

subtype axis128_saxis_o_t is axis_saxis_o_t;

subtype axis16_maxis_i_t is axis_maxis_i_t;

subtype axis16_saxis_o_t is axis_saxis_o_t;

subtype axis32_maxis_i_t is axis_maxis_i_t;

subtype axis32_saxis_o_t is axis_saxis_o_t;

subtype axis64_maxis_i_t is axis_maxis_i_t;

subtype axis64_saxis_o_t is axis_saxis_o_t;

subtype axis8_maxis_i_t is axis_maxis_i_t;

subtype axis8_saxis_o_t is axis_saxis_o_t;

constant AXIS128_MAXIS_O_NULL : axis128_maxis_o_t := (tvalid => '0', tdata => (others => '0'), tlast => '0');

constant AXIS128_SAXIS_I_NULL : axis128_saxis_i_t := (tvalid => '0', tdata => (others => '0'), tlast => '0');

constant AXIS16_MAXIS_O_NULL : axis16_maxis_o_t := (tvalid => '0', tdata => (others => '0'), tlast => '0');

constant AXIS16_SAXIS_I_NULL : axis16_saxis_i_t := (tvalid => '0', tdata => (others => '0'), tlast => '0');

constant AXIS32_MAXIS_O_NULL : axis32_maxis_o_t := (tvalid => '0', tdata => (others => '0'), tlast => '0');

constant AXIS32_SAXIS_I_NULL : axis32_saxis_i_t := (tvalid => '0', tdata => (others => '0'), tlast => '0');

constant AXIS64_MAXIS_O_NULL : axis64_maxis_o_t := (tvalid => '0', tdata => (others => '0'), tlast => '0');

constant AXIS64_SAXIS_I_NULL : axis64_saxis_i_t := (tvalid => '0', tdata => (others => '0'), tlast => '0');

constant AXIS8_MAXIS_O_NULL : axis8_maxis_o_t := (tvalid => '0', tdata => (others => '0'), tlast => '0');

constant AXIS8_SAXIS_I_NULL : axis8_saxis_i_t := (tvalid => '0', tdata => (others => '0'), tlast => '0');

constant AXIS_MAXIS_I_NULL : axis_maxis_i_t := (tready => '0');

constant AXIS_SAXIS_O_NULL : axis_saxis_o_t := (tready => '0');

function axis128_intf(aclk : std_logic; aresetn : std_logic; s : axis128_saxis_i_t; o : axis128_saxis_o_t) return axis128_intf_t;

function axis128_maxis_o(tvalid : std_logic; tdata : std_logic_vector(127 downto 0); tlast : std_logic) return axis128_maxis_o_t;

function axis128_saxis_i(tvalid : std_logic; tdata : std_logic_vector(127 downto 0); tlast : std_logic) return axis128_saxis_i_t;

function axis16_intf(aclk : std_logic; aresetn : std_logic; s : axis16_saxis_i_t; o : axis16_saxis_o_t) return axis16_intf_t;

function axis16_maxis_o(tvalid : std_logic; tdata : std_logic_vector(15 downto 0); tlast : std_logic) return axis16_maxis_o_t;

function axis16_saxis_i(tvalid : std_logic; tdata : std_logic_vector(15 downto 0); tlast : std_logic) return axis16_saxis_i_t;

function axis32_intf(aclk : std_logic; aresetn : std_logic; s : axis32_saxis_i_t; o : axis32_saxis_o_t) return axis32_intf_t;

function axis32_maxis_o(tvalid : std_logic; tdata : std_logic_vector(31 downto 0); tlast : std_logic) return axis32_maxis_o_t;

function axis32_saxis_i(tvalid : std_logic; tdata : std_logic_vector(31 downto 0); tlast : std_logic) return axis32_saxis_i_t;

function axis64_intf(aclk : std_logic; aresetn : std_logic; s : axis64_saxis_i_t; o : axis64_saxis_o_t) return axis64_intf_t;

function axis64_maxis_o(tvalid : std_logic; tdata : std_logic_vector(63 downto 0); tlast : std_logic) return axis64_maxis_o_t;

function axis64_saxis_i(tvalid : std_logic; tdata : std_logic_vector(63 downto 0); tlast : std_logic) return axis64_saxis_i_t;

function axis8_intf(aclk : std_logic; aresetn : std_logic; s : axis8_saxis_i_t; o : axis8_saxis_o_t) return axis8_intf_t;

function axis8_maxis_o(tvalid : std_logic; tdata : std_logic_vector(7 downto 0); tlast : std_logic) return axis8_maxis_o_t;

function axis8_saxis_i(tvalid : std_logic; tdata : std_logic_vector(7 downto 0); tlast : std_logic) return axis8_saxis_i_t;

function axis_maxis_i(tready : std_logic) return axis_maxis_i_t;

function axis_saxis_o(tready : std_logic) return axis_saxis_o_t;

type spi_intf_t is record sclk : std_logic; cs_n : std_logic; mosi : std_logic; miso : std_logic; end record;

type spi_master_i_t is record miso : std_logic; end record;

type spi_master_o_t is record sclk : std_logic; cs_n : std_logic; mosi : std_logic; end record;

type spi_slave_i_t is record sclk : std_logic; cs_n : std_logic; mosi : std_logic; end record;

type spi_slave_o_t is record miso : std_logic; end record;

type spi_slave_oe_t is record miso_oen : std_logic; end record;

constant SPI_MASTER_I_IDLE : spi_master_i_t := (miso => '0');

constant SPI_MASTER_O_IDLE : spi_master_o_t := (sclk => '0', cs_n => '1', mosi => '0');

constant SPI_SLAVE_I_IDLE : spi_slave_i_t := (sclk => '0', cs_n => '1', mosi => '0');

constant SPI_SLAVE_O_IDLE : spi_slave_o_t := (miso => '0');

constant SPI_SLAVE_OE_OFF : spi_slave_oe_t := (miso_oen => '1');

function spi_intf(master_o : spi_master_o_t; master_i : spi_master_i_t) return spi_intf_t;

function spi_master_i(miso : std_logic) return spi_master_i_t;

function spi_master_i(intf : spi_intf_t) return spi_master_i_t;

function spi_master_o(sclk : std_logic; cs_n : std_logic; mosi : std_logic) return spi_master_o_t;

function spi_master_o(intf : spi_intf_t) return spi_master_o_t;

function spi_slave_i(sclk : std_logic; cs_n : std_logic; mosi : std_logic) return spi_slave_i_t;

function spi_slave_i(intf : spi_intf_t) return spi_slave_i_t;

function spi_slave_o(miso : std_logic) return spi_slave_o_t;

function spi_slave_o(intf : spi_intf_t) return spi_slave_o_t;

function spi_slave_oe(miso_oen : std_logic) return spi_slave_oe_t;