{
  "backend": "ghdl",
  "testbench": "tb_radila_core",
  "status": "passed",
  "libraries": [
    "radila"
  ],
  "analyzed": {
    "xpm": [
      "sim/xpm/xpm_memory_models.vhd"
    ],
    "radila": [
      "common/hdl/src/radhdl_axis_pkg.vhd",
      "common/hdl/src/radhdl_spi_pkg.vhd",
      "common/hdl/src/radhdl_axi_pkg.vhd",
      "debug/radila/hdl/radila/radila_core.vhd",
      "debug/radila/hdl/radila/raddebughub.vhd"
    ],
    "work": [
      "debug/radila/hdl/radila/radila_core.vhd",
      "debug/radila/hdl/radila/raddebughub.vhd",
      "debug/radila/hdl/radila/testbenches/tb_radila_core.vhd"
    ]
  },
  "vcd": "simulations/tb_radila_core/tb_radila_core.vcd",
  "stdout": "debug/radila/hdl/radila/testbenches/tb_radila_core.vhd:173:5:@8085ns:(report note): tb_radila_core passed\nsimulation finished @8085ns\n",
  "stderr": ""
}