radila_gowin_dpb_ram

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.debug.all;

Component Declaration

component radila_gowin_dpb_ram is
  generic (
    DATA_WIDTH : positive := 64;
    ADDR_WIDTH : positive := 8
  );
  port (
    wr_clk : in std_logic;
    wr_rst : in std_logic;
    wr_en : in std_logic;
    wr_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
    wr_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    rd_clk : in std_logic;
    rd_rst : in std_logic;
    rd_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
    rd_data : out std_logic_vector(DATA_WIDTH - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_radila_gowin_dpb_ram : entity radhdl.radila_gowin_dpb_ram
  generic map (
    DATA_WIDTH => 64,
    ADDR_WIDTH => 8
  )
  port map (
    wr_clk  => <wr_clk_signal>,
    wr_rst  => <wr_rst_signal>,
    wr_en   => <wr_en_signal>,
    wr_addr => <wr_addr_signal>,
    wr_data => <wr_data_signal>,
    rd_clk  => <rd_clk_signal>,
    rd_rst  => <rd_rst_signal>,
    rd_addr => <rd_addr_signal>,
    rd_data => <rd_data_signal>
  );