RadILA Datasheet

Use Cases

Debug and observability hooks for generated FPGA systems.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.debug.all;

Component Declaration

component RadILA is
  generic (
    SAMPLE_WIDTH : integer := 32;
    EVENT_WIDTH : integer := 8;
    DEPTH : integer := 1024;
    ADDR_WIDTH : integer := 10;
    CMD_LANES : integer := 4;
    VENDOR_TAG : string := "XILINX";
    PRODUCT_SERIES_TAG : string := "7SERIES"
  );
  port (
    axi_clk : in std_logic;
    axi_rstn : in std_logic;
    sample_clk : in std_logic;
    sample_rstn : in std_logic;
    sample_i : in std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    event_i : in std_logic_vector(EVENT_WIDTH - 1 downto 0);
    cmd_data_i : in std_logic_vector(CMD_LANES - 1 downto 0);
    cmd_toggle_i : in std_logic;
    cmd_ack_toggle_o : out std_logic;
    rd_index_i : in unsigned(ADDR_WIDTH - 1 downto 0);
    rd_data_o : out std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    sample_now_o : out std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
    event_now_o : out std_logic_vector(EVENT_WIDTH - 1 downto 0);
    armed_o : out std_logic;
    capturing_o : out std_logic;
    done_o : out std_logic;
    overflow_o : out std_logic;
    count_o : out unsigned(ADDR_WIDTH downto 0)
  );
end component;

Direct Entity Instantiation

u_radila : entity radhdl.RadILA
  generic map (
    SAMPLE_WIDTH       => 32,
    EVENT_WIDTH        => 8,
    DEPTH              => 1024,
    ADDR_WIDTH         => 10,
    CMD_LANES          => 4,
    VENDOR_TAG         => "XILINX",
    PRODUCT_SERIES_TAG => "7SERIES"
  )
  port map (
    axi_clk          => <axi_clk_signal>,
    axi_rstn         => <axi_rstn_signal>,
    sample_clk       => <sample_clk_signal>,
    sample_rstn      => <sample_rstn_signal>,
    sample_i         => <sample_i_signal>,
    event_i          => <event_i_signal>,
    cmd_data_i       => <cmd_data_i_signal>,
    cmd_toggle_i     => <cmd_toggle_i_signal>,
    cmd_ack_toggle_o => <cmd_ack_toggle_o_signal>,
    rd_index_i       => <rd_index_i_signal>,
    rd_data_o        => <rd_data_o_signal>,
    sample_now_o     => <sample_now_o_signal>,
    event_now_o      => <event_now_o_signal>,
    armed_o          => <armed_o_signal>,
    capturing_o      => <capturing_o_signal>,
    done_o           => <done_o_signal>,
    overflow_o       => <overflow_o_signal>,
    count_o          => <count_o_signal>
  );

Generics

Name	Type	Default	Description
SAMPLE_WIDTH	integer	32	Sets the bit width for SAMPLE WIDTH values carried by this module.
EVENT_WIDTH	integer	8	Sets the bit width for EVENT WIDTH values carried by this module.
DEPTH	integer	1024	Sets the storage depth, frame length, or number of buffered samples used internally.
ADDR_WIDTH	integer	10	Sets the bit width for ADDR WIDTH values carried by this module.
CMD_LANES	integer	4	Sets the number of parallel sample lanes processed per handshake beat.
VENDOR_TAG	string	"XILINX"	Selects the vendor-specific implementation path, usually XILINX for DSP48/XPM-backed builds or generic for portable RTL.
PRODUCT_SERIES_TAG	string	"7SERIES"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.

Ports

Name	Direction	Type	Description
axi_clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
axi_rstn	in	std_logic	Active-low reset for this clock domain.
sample_clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
sample_rstn	in	std_logic	Active-low reset for this clock domain.
sample_i	in	std_logic_vector(SAMPLE_WIDTH - 1 downto 0)	Input sample vector captured or processed by the datapath.
event_i	in	std_logic_vector(EVENT_WIDTH - 1 downto 0)	Event or trigger metadata associated with the current sample stream.
cmd_data_i	in	std_logic_vector(CMD_LANES - 1 downto 0)	Command/control input used to configure or trigger the block.
cmd_toggle_i	in	std_logic	Command/control input used to configure or trigger the block.
cmd_ack_toggle_o	out	std_logic	Command/control acknowledgement or status output.
rd_index_i	in	unsigned(ADDR_WIDTH - 1 downto 0)	Readback control or data signal for host-visible captured state.
rd_data_o	out	std_logic_vector(SAMPLE_WIDTH - 1 downto 0)	Readback control or data signal for host-visible captured state.
sample_now_o	out	std_logic_vector(SAMPLE_WIDTH - 1 downto 0)	Output sample vector or current sample status from the datapath.
event_now_o	out	std_logic_vector(EVENT_WIDTH - 1 downto 0)	Event or trigger metadata associated with the current sample stream.
armed_o	out	std_logic	Output armed o signal generated by this module.
capturing_o	out	std_logic	Output capturing o signal generated by this module.
done_o	out	std_logic	Output done o signal generated by this module.
overflow_o	out	std_logic	Output overflow o signal generated by this module.
count_o	out	unsigned(ADDR_WIDTH downto 0)	Output count o signal generated by this module.

Register Interfaces

No fixed register map was found; this section documents the exposed register/control interface ports.

Interface	Directions	Signals	Representative ports
Register control/status	in, out	2	rd_index_i, rd_data_o

Testbenches

tb_radila_core interface timing diagram

Source: debug/radila/hdl/radila/testbenches/tb_radila_core.vhd

Self-checking or stimulus-focused testbench for radila core. Exercises representative handshakes, reset behavior, frame boundaries, and numeric corner cases for regression runs.

Interface Timing Diagram

Source: debug/radila/hdl/radila/testbenches/tb_radila_core.vhd

Horizontal Vertical

axi_clk

sample_clk

axi_rstn

sample_rstn

done_o

cmd_data_i

count_o

rd_data_o

armed_o

capturing_o

cmd_ack_toggle_o

cmd_toggle_i

event_i

event_now_o

overflow_o

rd_index_i

sample_i

sample_now_o

Sources

debug/radila/hdl/radila/radila_core.vhd