radif_uart_to_reg

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_uart.all;

Component Declaration

component radif_uart_to_reg is
  generic (
    DATA_WIDTH : integer := 32;
    ADDR_WIDTH : integer := 16;
    BAUD_DIVISOR : positive := 868;
    VENDOR_TAG : string := "GENERIC";
    PRODUCT_SERIES_TAG : string := "GENERIC"
  );
  port (
    clk : in std_logic;
    rstn : in std_logic;
    uart_rx_i : in std_logic;
    uart_tx_o : out std_logic;
    reg_wr_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
    reg_rd_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
    reg_wr_en : out std_logic;
    reg_rd_en : out std_logic;
    reg_data_in : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_wr_rdy : in std_logic;
    reg_rd_rdy : in std_logic;
    reg_wr_valid : in std_logic;
    reg_rd_valid : in std_logic;
    reg_error : in std_logic
  );
end component;

Direct Entity Instantiation

u_radif_uart_to_reg : entity radhdl.radif_uart_to_reg
  generic map (
    DATA_WIDTH         => 32,
    ADDR_WIDTH         => 16,
    BAUD_DIVISOR       => 868,
    VENDOR_TAG         => "GENERIC",
    PRODUCT_SERIES_TAG => "GENERIC"
  )
  port map (
    clk          => <clk_signal>,
    rstn         => <rstn_signal>,
    uart_rx_i    => <uart_rx_i_signal>,
    uart_tx_o    => <uart_tx_o_signal>,
    reg_wr_addr  => <reg_wr_addr_signal>,
    reg_rd_addr  => <reg_rd_addr_signal>,
    reg_wr_en    => <reg_wr_en_signal>,
    reg_rd_en    => <reg_rd_en_signal>,
    reg_data_in  => <reg_data_in_signal>,
    reg_data_out => <reg_data_out_signal>,
    reg_wr_rdy   => <reg_wr_rdy_signal>,
    reg_rd_rdy   => <reg_rd_rdy_signal>,
    reg_wr_valid => <reg_wr_valid_signal>,
    reg_rd_valid => <reg_rd_valid_signal>,
    reg_error    => <reg_error_signal>
  );