radif_reg_to_spi_master Datasheet

Use Cases

Memory-mapped control/status integration with software-visible register maps.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_spi.all;

Component Declaration

component radif_reg_to_spi_master is
  generic (
    DATA_WIDTH : positive := 32;
    REG_ADDR_WIDTH : positive := 16;
    DEFAULT_SCLK_DIV : natural := 124;
    DEFAULT_BIT_COUNT : positive := 8;
    VENDOR_TAG : string := "GENERIC";
    PRODUCT_SERIES_TAG : string := "GENERIC"
  );
  port (
    clk : in std_logic;
    rstn : in std_logic;
    reg_wr_addr : in std_logic_vector(REG_ADDR_WIDTH - 1 downto 0);
    reg_rd_addr : in std_logic_vector(REG_ADDR_WIDTH - 1 downto 0);
    reg_wr_en : in std_logic;
    reg_rd_en : in std_logic;
    reg_data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_wr_rdy : out std_logic;
    reg_rd_rdy : out std_logic;
    reg_wr_valid : out std_logic;
    reg_rd_valid : out std_logic;
    reg_error : out std_logic;
    spi_sclk_o : out std_logic;
    spi_cs_n_o : out std_logic;
    spi_mosi_o : out std_logic;
    spi_miso_i : in std_logic
  );
end component;

Direct Entity Instantiation

u_radif_reg_to_spi_master : entity radhdl.radif_reg_to_spi_master
  generic map (
    DATA_WIDTH         => 32,
    REG_ADDR_WIDTH     => 16,
    DEFAULT_SCLK_DIV   => 124,
    DEFAULT_BIT_COUNT  => 8,
    VENDOR_TAG         => "GENERIC",
    PRODUCT_SERIES_TAG => "GENERIC"
  )
  port map (
    clk          => <clk_signal>,
    rstn         => <rstn_signal>,
    reg_wr_addr  => <reg_wr_addr_signal>,
    reg_rd_addr  => <reg_rd_addr_signal>,
    reg_wr_en    => <reg_wr_en_signal>,
    reg_rd_en    => <reg_rd_en_signal>,
    reg_data_in  => <reg_data_in_signal>,
    reg_data_out => <reg_data_out_signal>,
    reg_wr_rdy   => <reg_wr_rdy_signal>,
    reg_rd_rdy   => <reg_rd_rdy_signal>,
    reg_wr_valid => <reg_wr_valid_signal>,
    reg_rd_valid => <reg_rd_valid_signal>,
    reg_error    => <reg_error_signal>,
    spi_sclk_o   => <spi_sclk_o_signal>,
    spi_cs_n_o   => <spi_cs_n_o_signal>,
    spi_mosi_o   => <spi_mosi_o_signal>,
    spi_miso_i   => <spi_miso_i_signal>
  );

Generics

Name	Type	Default	Description
DATA_WIDTH	positive	32	Width of the RADIF register data bus and the maximum SPI transfer word.
REG_ADDR_WIDTH	positive	16	Width of the RADIF register address bus.
DEFAULT_SCLK_DIV	natural	124	Default half-period divider for SCLK generation. The active half-period is divider + 1 FPGA clock cycles.
DEFAULT_BIT_COUNT	positive	8	Default number of bits shifted per transfer.
VENDOR_TAG	string	"GENERIC"	Selects the vendor-specific implementation path. This core is portable RTL for all values.
PRODUCT_SERIES_TAG	string	"GENERIC"	Identifies the target FPGA family for generated project metadata.

Ports

Name	Direction	Type	Description
clk	in	std_logic	FPGA/register clock domain.
rstn	in	std_logic	Active-low reset for the FPGA/register clock domain.
reg_wr_addr	in	std_logic_vector(REG_ADDR_WIDTH - 1 downto 0)	Register write address.
reg_rd_addr	in	std_logic_vector(REG_ADDR_WIDTH - 1 downto 0)	Register read address.
reg_wr_en	in	std_logic	One-cycle register write request.
reg_rd_en	in	std_logic	One-cycle register read request.
reg_data_in	in	std_logic_vector(DATA_WIDTH - 1 downto 0)	Register write data.
reg_data_out	out	std_logic_vector(DATA_WIDTH - 1 downto 0)	Register read data.
reg_wr_rdy	out	std_logic	Register write ready.
reg_rd_rdy	out	std_logic	Register read ready.
reg_wr_valid	out	std_logic	Register write response valid.
reg_rd_valid	out	std_logic	Register read response valid.
reg_error	out	std_logic	Register address or transaction error.
spi_sclk_o	out	std_logic	SPI serial clock.
spi_cs_n_o	out	std_logic	SPI chip select, active low by default.
spi_mosi_o	out	std_logic	SPI master-out/slave-in data.
spi_miso_i	in	std_logic	SPI master-in/slave-out data sampled into the RX_DATA register.

Measured Implementation Metrics

Metrics are generated by RadBuild from real Vivado synthesis reports for representative device targets. Raw report paths are preserved in the checked summary JSON.

Part	Clock ns	MHz	LUTs	FFs	BRAM tiles	DSPs	Setup WNS ns	Hold WHS ns	Generics	Summary
xc7z020clg400-1	10.0	100.0	202	272	0	0	5.704	0.152	-	projects/synth_reports/radif_reg_to_spi_master/xc7z020clg400-1/synth_summary.json

Register Interfaces

Static register maps are rendered below for this module.

Interface	Directions	Signals	Representative ports
Register control/status	in, out	11	reg_wr_addr, reg_rd_addr, reg_wr_en, reg_rd_en, reg_data_in, reg_data_out, reg_wr_rdy, reg_rd_rdy, +3 more

Register Maps

radif_reg_to_spi_master

Source: interfaces/hdl/radif/register_maps/radif_reg_to_spi_master.map.json

Controls single-word SPI transfers, SCLK timing, transfer width, and SPI mode.

Register	Offset	Access	Reset	Description
control	0x00	rw	0x00000000	Launches single-word SPI transfers and clears sticky completion/error status.
status	0x04	ro	0x00000000	Reports current SPI transfer state and sticky completion/error status.
clk_div	0x08	rw	DEFAULT_SCLK_DIV	Configures the SPI SCLK timing derived from the FPGA/register clock.
config	0x0C	rw	DEFAULT_BIT_COUNT << 8	Configures SPI clock mode, chip-select polarity, and transfer width.
tx_data	0x10	rw	0x00000000	Stores the MSB-first MOSI transmit word used by the next SPI transfer. Reads return the transmit holding register, not sampled MISO data.
rx_data	0x14	ro	0x00000000	Returns the MSB-first MISO receive word captured by the most recent SPI transfer.

control

Offset 0x00 / Access rw / Reset 0x00000000

Launches single-word SPI transfers and clears sticky completion/error status.

Control[15:0]

1514131211109876543210

RSVD [15:2]

CLEAR

START

Control[31:16]

31302928272625242322212019181716

RSVD [31:16]

Name	Register bit(s)	Description
CLEAR	Control[1]	Writing 1 clears STATUS.DONE and STATUS.ERR. Software should write this as a pulse when it wants fresh transaction status.
START	Control[0]	Writing 1 starts a SPI transfer when the master is idle. The transfer uses CONFIG, CLK_DIV, and TX_DATA values already written before START.

status

Offset 0x04 / Access ro / Reset 0x00000000

Reports current SPI transfer state and sticky completion/error status.

Status[15:0]

1514131211109876543210

RSVD [15:3]

ERR

DONE

BUSY

Status[31:16]

31302928272625242322212019181716

RSVD [31:16]

Name	Register bit(s)	Description
ERR	Status[2]	Sticky error bit set when START is requested while BUSY or an unsupported register access is attempted.
DONE	Status[1]	Sticky completion bit set after the configured number of bits has been shifted and chip select is released.
BUSY	Status[0]	Set while chip select is asserted or bits are actively being shifted on SCLK.

clk_div

Offset 0x08 / Access rw / Reset DEFAULT_SCLK_DIV

Configures the SPI SCLK timing derived from the FPGA/register clock.

ClkDiv[15:0]

1514131211109876543210

SCLK DIV [15:0]

ClkDiv[31:16]

31302928272625242322212019181716

RSVD [31:16]

Name	Register bit(s)	Description
SCLK DIV	ClkDiv[15:0]	SCLK half-period divider. The generated SCLK phase changes every SCLK_DIV + 1 FPGA clock cycles.

config

Offset 0x0C / Access rw / Reset DEFAULT_BIT_COUNT << 8

Configures SPI clock mode, chip-select polarity, and transfer width.

Config[15:0]

1514131211109876543210

BIT COUNT [15:8]

RSVD [7:3]

CS ACTIVE HIGH

CPHA

CPOL

Config[31:16]

31302928272625242322212019181716

RSVD [31:16]

Name	Register bit(s)	Description
BIT COUNT	Config[15:8]	Number of bits shifted during each transfer. Values below 1 clamp to 1 and values above DATA_WIDTH clamp to DATA_WIDTH.
CS ACTIVE HIGH	Config[2]	Chip-select polarity selector. 0 drives spi_cs_n_o low during transfers, 1 inverts the output polarity for active-high chip-select wiring.
CPHA	Config[1]	SPI clock phase. 0 samples MISO on the first active clock edge, 1 samples MISO on the second active clock edge.
CPOL	Config[0]	SPI clock polarity. 0 idles SCLK low, 1 idles SCLK high.

tx_data

Offset 0x10 / Access rw / Reset 0x00000000

Stores the MSB-first MOSI transmit word used by the next SPI transfer. Reads return the transmit holding register, not sampled MISO data.

TxData[15:0]

1514131211109876543210

TX WORD [15:0]

TxData[31:16]

31302928272625242322212019181716

TX WORD [31:16]

Name	Register bit(s)	Description
TX WORD	TxData[31:0]	MOSI transmit shift word. The core begins with TX_WORD[31], so transfers shorter than 32 bits should place the intended output payload in the most-significant bits.

rx_data

Offset 0x14 / Access ro / Reset 0x00000000

Returns the MSB-first MISO receive word captured by the most recent SPI transfer.

RxData[15:0]

1514131211109876543210

RX WORD [15:0]

RxData[31:16]

31302928272625242322212019181716

RX WORD [31:16]

Name	Register bit(s)	Description
RX WORD	RxData[31:0]	MISO receive shift word. For transfers shorter than 32 bits, sampled input bits are accumulated into the least-significant bits in transfer order after the configured number of clocks.

Testbenches

tb_radif_reg_to_spi_master interface timing diagram

Source: interfaces/hdl/radif/testbenches/tb_radif_reg_to_spi_master.vhd

Exercises the register-controlled 4-wire SPI master with a looped-back MISO/MOSI path. The waveform shows software register writes, chip-select assertion, generated SCLK pulses, MOSI output shifting, MISO input sampling, and transaction completion status.

Interface Timing Diagram

Source: interfaces/hdl/radif/testbenches/tb_radif_reg_to_spi_master.vhd

Horizontal Vertical

clk

rstn

reg_rd_valid

reg_wr_valid

reg_data_in

reg_data_out

reg_rd_addr

reg_wr_addr

reg_error

reg_rd_en

reg_rd_rdy

reg_wr_en

reg_wr_rdy

SPI

SPI interface signals

SPI Interface Waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_reg_to_spi_master.vhd

Horizontal Vertical

spi_sclk_o

spi_cs_n_o

spi_miso_i

spi_mosi_o

Sources

interfaces/hdl/radif/src/radif_reg_to_spi_master.vhd