radif_reg_to_i2c_master Datasheet

Use Cases

Memory-mapped control/status integration with software-visible register maps.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_i2c.all;

Component Declaration

component radif_reg_to_i2c_master is
  generic (
    DATA_WIDTH : positive := 32;
    REG_ADDR_WIDTH : positive := 16;
    DEFAULT_SCL_DIV : natural := 124;
    VENDOR_TAG : string := "GENERIC";
    PRODUCT_SERIES_TAG : string := "GENERIC"
  );
  port (
    clk : in std_logic;
    rstn : in std_logic;
    reg_wr_addr : in std_logic_vector(REG_ADDR_WIDTH - 1 downto 0);
    reg_rd_addr : in std_logic_vector(REG_ADDR_WIDTH - 1 downto 0);
    reg_wr_en : in std_logic;
    reg_rd_en : in std_logic;
    reg_data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_wr_rdy : out std_logic;
    reg_rd_rdy : out std_logic;
    reg_wr_valid : out std_logic;
    reg_rd_valid : out std_logic;
    reg_error : out std_logic;
    i2c_scl_i : in std_logic;
    i2c_sda_i : in std_logic;
    i2c_scl_oen : out std_logic;
    i2c_sda_oen : out std_logic
  );
end component;

Direct Entity Instantiation

u_radif_reg_to_i2c_master : entity radhdl.radif_reg_to_i2c_master
  generic map (
    DATA_WIDTH         => 32,
    REG_ADDR_WIDTH     => 16,
    DEFAULT_SCL_DIV    => 124,
    VENDOR_TAG         => "GENERIC",
    PRODUCT_SERIES_TAG => "GENERIC"
  )
  port map (
    clk          => <clk_signal>,
    rstn         => <rstn_signal>,
    reg_wr_addr  => <reg_wr_addr_signal>,
    reg_rd_addr  => <reg_rd_addr_signal>,
    reg_wr_en    => <reg_wr_en_signal>,
    reg_rd_en    => <reg_rd_en_signal>,
    reg_data_in  => <reg_data_in_signal>,
    reg_data_out => <reg_data_out_signal>,
    reg_wr_rdy   => <reg_wr_rdy_signal>,
    reg_rd_rdy   => <reg_rd_rdy_signal>,
    reg_wr_valid => <reg_wr_valid_signal>,
    reg_rd_valid => <reg_rd_valid_signal>,
    reg_error    => <reg_error_signal>,
    i2c_scl_i    => <i2c_scl_i_signal>,
    i2c_sda_i    => <i2c_sda_i_signal>,
    i2c_scl_oen  => <i2c_scl_oen_signal>,
    i2c_sda_oen  => <i2c_sda_oen_signal>
  );

Generics

Name	Type	Default	Description
DATA_WIDTH	positive	32	Width of the RADIF register data bus.
REG_ADDR_WIDTH	positive	16	Width of the RADIF register address bus.
DEFAULT_SCL_DIV	natural	124	Default SCL half-period divider. The active half-period is divider + 1 FPGA clock cycles.
VENDOR_TAG	string	"GENERIC"	Selects the vendor-specific implementation path. This core is portable RTL for all values.
PRODUCT_SERIES_TAG	string	"GENERIC"	Identifies the target FPGA family for generated project metadata.

Ports

Name	Direction	Type	Description
clk	in	std_logic	FPGA/register clock domain.
rstn	in	std_logic	Active-low reset for the FPGA/register clock domain.
reg_wr_addr	in	std_logic_vector(REG_ADDR_WIDTH - 1 downto 0)	Register write address.
reg_rd_addr	in	std_logic_vector(REG_ADDR_WIDTH - 1 downto 0)	Register read address.
reg_wr_en	in	std_logic	One-cycle register write request.
reg_rd_en	in	std_logic	One-cycle register read request.
reg_data_in	in	std_logic_vector(DATA_WIDTH - 1 downto 0)	Register write data.
reg_data_out	out	std_logic_vector(DATA_WIDTH - 1 downto 0)	Register read data.
reg_wr_rdy	out	std_logic	Register write ready.
reg_rd_rdy	out	std_logic	Register read ready.
reg_wr_valid	out	std_logic	Register write response valid.
reg_rd_valid	out	std_logic	Register read response valid.
reg_error	out	std_logic	Register address or transaction error.
i2c_scl_i	in	std_logic	Open-drain SCL input as observed at the pin.
i2c_sda_i	in	std_logic	Open-drain SDA input as observed at the pin.
i2c_scl_oen	out	std_logic	SCL output-enable. A value of 0 drives SCL low; a value of 1 releases SCL.
i2c_sda_oen	out	std_logic	SDA output-enable. A value of 0 drives SDA low; a value of 1 releases SDA.

Register Interfaces

Static register maps are rendered below for this module.

Interface	Directions	Signals	Representative ports
Register control/status	in, out	11	reg_wr_addr, reg_rd_addr, reg_wr_en, reg_rd_en, reg_data_in, reg_data_out, reg_wr_rdy, reg_rd_rdy, +3 more

Register Maps

radif_reg_to_i2c_master

Source: interfaces/hdl/radif/register_maps/radif_reg_to_i2c_master.map.json

Controls one-byte I2C read/write transactions and SCL timing.

Register	Offset	Access	Reset	Description
control	0x00	rw	0x00000000	Launches one-byte I2C transactions and clears sticky completion/error status.
status	0x04	ro	0x00000000	Reports current I2C transaction state and sticky completion/error status.
clk_div	0x08	rw	DEFAULT_SCL_DIV	Configures the I2C SCL phase timing derived from the FPGA/register clock.
slave_addr	0x0C	rw	0x00000000	Stores the 7-bit I2C target address used by the next transaction.
tx_data	0x10	rw	0x00000000	Stores the data byte used by the next I2C write transaction.
rx_data	0x14	ro	0x00000000	Returns the data byte captured by the most recent I2C read transaction.

control

Offset 0x00 / Access rw / Reset 0x00000000

Launches one-byte I2C transactions and clears sticky completion/error status.

Control[15:0]

1514131211109876543210

RSVD [15:3]

READ

CLEAR

START

Control[31:16]

31302928272625242322212019181716

RSVD [31:16]

Name	Register bit(s)	Description
READ	Control[2]	Selects transaction direction. 1 performs an I2C byte read from SLAVE_ADDR, 0 performs an I2C byte write using TX_DATA.
CLEAR	Control[1]	Writing 1 clears STATUS.DONE and STATUS.ACK_ERR. Software should write this as a pulse before launching another transaction when it wants fresh status.
START	Control[0]	Writing 1 starts a one-byte I2C transaction when the master is idle. START is ignored as a stored level by transaction logic after the launch cycle.

status

Offset 0x04 / Access ro / Reset 0x00000000

Reports current I2C transaction state and sticky completion/error status.

Status[15:0]

1514131211109876543210

RSVD [15:3]

ACK ERR

DONE

BUSY

Status[31:16]

31302928272625242322212019181716

RSVD [31:16]

Name	Register bit(s)	Description
ACK ERR	Status[2]	Sticky error bit set when the target does not acknowledge the address byte or write data byte, or when START is requested while BUSY.
DONE	Status[1]	Sticky completion bit set when the most recent transaction reaches STOP. Cleared by CONTROL.CLEAR, a new START, or reset.
BUSY	Status[0]	Set while the I2C state machine is actively generating START, address, data, acknowledge, or STOP phases.

clk_div

Offset 0x08 / Access rw / Reset DEFAULT_SCL_DIV

Configures the I2C SCL phase timing derived from the FPGA/register clock.

ClkDiv[15:0]

1514131211109876543210

SCL DIV [15:0]

ClkDiv[31:16]

31302928272625242322212019181716

RSVD [31:16]

Name	Register bit(s)	Description
SCL DIV	ClkDiv[15:0]	SCL half-period divider. The I2C state machine advances each SCL phase every SCL_DIV + 1 FPGA clock cycles.

slave_addr

Offset 0x0C / Access rw / Reset 0x00000000

Stores the 7-bit I2C target address used by the next transaction.

SlaveAddr[15:0]

1514131211109876543210

RSVD [15:7]

SLAVE ADDR [6:0]

SlaveAddr[31:16]

31302928272625242322212019181716

RSVD [31:16]

Name	Register bit(s)	Description
SLAVE ADDR	SlaveAddr[6:0]	Unshifted 7-bit I2C slave address. The core appends CONTROL.READ as the R/W bit during the address phase.

tx_data

Offset 0x10 / Access rw / Reset 0x00000000

Stores the data byte used by the next I2C write transaction.

TxData[15:0]

1514131211109876543210

RSVD [15:8]

TX BYTE [7:0]

TxData[31:16]

31302928272625242322212019181716

RSVD [31:16]

Name	Register bit(s)	Description
TX BYTE	TxData[7:0]	One byte transmitted after the slave address when CONTROL.READ is 0.

rx_data

Offset 0x14 / Access ro / Reset 0x00000000

Returns the data byte captured by the most recent I2C read transaction.

RxData[15:0]

1514131211109876543210

RSVD [15:8]

RX BYTE [7:0]

RxData[31:16]

31302928272625242322212019181716

RSVD [31:16]

Name	Register bit(s)	Description
RX BYTE	RxData[7:0]	One byte sampled from SDA during the data phase when CONTROL.READ is 1.

Testbenches

tb_radif_reg_to_i2c_master interface timing diagram

Source: interfaces/hdl/radif/testbenches/tb_radif_reg_to_i2c_master.vhd

Exercises the register-controlled I2C master with always-acknowledging open-drain bus behavior. The waveform shows register launch, START, address byte, write data byte, ACK sampling, STOP, and completion status.

Interface Timing Diagram

Source: interfaces/hdl/radif/testbenches/tb_radif_reg_to_i2c_master.vhd

Horizontal Vertical

clk

rstn

reg_rd_valid

reg_wr_valid

reg_data_in

reg_data_out

reg_rd_addr

reg_wr_addr

reg_error

reg_rd_en

reg_rd_rdy

reg_wr_en

reg_wr_rdy

I2C

I2C interface signals

I2C Interface Waveform

Source: interfaces/hdl/radif/testbenches/tb_radif_reg_to_i2c_master.vhd

Horizontal Vertical

i2c_scl_i

i2c_scl_oen

i2c_sda_i

i2c_sda_oen

Sources

interfaces/hdl/radif/src/radif_reg_to_i2c_master.vhd