radif_reg_interconnect Datasheet

Use Cases

Memory-mapped control/status integration with software-visible register maps.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_regbank.all;

Component Declaration

component radif_reg_interconnect is
  generic (
    DATA_WIDTH : integer := 32;
    ADDR_WIDTH : integer := 16;
    SLAVE_COUNT : integer := 2;
    SLAVE_BASE_ADDRS : std_logic_vector((SLAVE_COUNT * ADDR_WIDTH) - 1 downto 0) := x"00000000";
    SLAVE_ADDR_MASKS : std_logic_vector((SLAVE_COUNT * ADDR_WIDTH) - 1 downto 0) := x"F000F000";
    VENDOR_TAG : string := "XILINX";
    PRODUCT_SERIES_TAG : string := "GENERIC"
  );
  port (
    clk : in std_logic;
    rstn : in std_logic;
    wr_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
    rd_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
    wr_en_i : in std_logic;
    rd_en_i : in std_logic;
    data_in_i : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    data_out_o : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    wr_rdy_o : out std_logic;
    rd_rdy_o : out std_logic;
    wr_valid_o : out std_logic;
    rd_valid_o : out std_logic;
    error_o : out std_logic;
    s_wr_addr_o : out std_logic_vector((SLAVE_COUNT * ADDR_WIDTH) - 1 downto 0);
    s_rd_addr_o : out std_logic_vector((SLAVE_COUNT * ADDR_WIDTH) - 1 downto 0);
    s_wr_en_o : out std_logic_vector(SLAVE_COUNT - 1 downto 0);
    s_rd_en_o : out std_logic_vector(SLAVE_COUNT - 1 downto 0);
    s_data_in_o : out std_logic_vector((SLAVE_COUNT * DATA_WIDTH) - 1 downto 0);
    s_data_out_i : in std_logic_vector((SLAVE_COUNT * DATA_WIDTH) - 1 downto 0);
    s_wr_rdy_i : in std_logic_vector(SLAVE_COUNT - 1 downto 0);
    s_rd_rdy_i : in std_logic_vector(SLAVE_COUNT - 1 downto 0);
    s_wr_valid_i : in std_logic_vector(SLAVE_COUNT - 1 downto 0);
    s_rd_valid_i : in std_logic_vector(SLAVE_COUNT - 1 downto 0);
    s_error_i : in std_logic_vector(SLAVE_COUNT - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_radif_reg_interconnect : entity radhdl.radif_reg_interconnect
  generic map (
    DATA_WIDTH         => 32,
    ADDR_WIDTH         => 16,
    SLAVE_COUNT        => 2,
    SLAVE_BASE_ADDRS   => x"00000000",
    SLAVE_ADDR_MASKS   => x"F000F000",
    VENDOR_TAG         => "XILINX",
    PRODUCT_SERIES_TAG => "GENERIC"
  )
  port map (
    clk          => <clk_signal>,
    rstn         => <rstn_signal>,
    wr_addr_i    => <wr_addr_i_signal>,
    rd_addr_i    => <rd_addr_i_signal>,
    wr_en_i      => <wr_en_i_signal>,
    rd_en_i      => <rd_en_i_signal>,
    data_in_i    => <data_in_i_signal>,
    data_out_o   => <data_out_o_signal>,
    wr_rdy_o     => <wr_rdy_o_signal>,
    rd_rdy_o     => <rd_rdy_o_signal>,
    wr_valid_o   => <wr_valid_o_signal>,
    rd_valid_o   => <rd_valid_o_signal>,
    error_o      => <error_o_signal>,
    s_wr_addr_o  => <s_wr_addr_o_signal>,
    s_rd_addr_o  => <s_rd_addr_o_signal>,
    s_wr_en_o    => <s_wr_en_o_signal>,
    s_rd_en_o    => <s_rd_en_o_signal>,
    s_data_in_o  => <s_data_in_o_signal>,
    s_data_out_i => <s_data_out_i_signal>,
    s_wr_rdy_i   => <s_wr_rdy_i_signal>,
    s_rd_rdy_i   => <s_rd_rdy_i_signal>,
    s_wr_valid_i => <s_wr_valid_i_signal>,
    s_rd_valid_i => <s_rd_valid_i_signal>,
    s_error_i    => <s_error_i_signal>
  );

Generics

Name	Type	Default	Description
DATA_WIDTH	integer	32	Sets the bit width for DATA WIDTH values carried by this module.
ADDR_WIDTH	integer	16	Sets the bit width for ADDR WIDTH values carried by this module.
SLAVE_COUNT	integer	2	Configures SLAVE COUNT for this instance.
SLAVE_BASE_ADDRS	std_logic_vector((SLAVE_COUNT * ADDR_WIDTH) - 1 downto 0)	x"00000000"	Configures SLAVE BASE ADDRS for this instance.
SLAVE_ADDR_MASKS	std_logic_vector((SLAVE_COUNT * ADDR_WIDTH) - 1 downto 0)	x"F000F000"	Configures SLAVE ADDR MASKS for this instance.
VENDOR_TAG	string	"XILINX"	Selects the vendor-specific implementation path, usually XILINX for DSP48/XPM-backed builds or generic for portable RTL.
PRODUCT_SERIES_TAG	string	"GENERIC"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.

Ports

Name	Direction	Type	Description
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rstn	in	std_logic	Active-low reset for this clock domain.
wr_addr_i	in	std_logic_vector(ADDR_WIDTH - 1 downto 0)	Input wr addr i signal for this module.
rd_addr_i	in	std_logic_vector(ADDR_WIDTH - 1 downto 0)	Readback control or data signal for host-visible captured state.
wr_en_i	in	std_logic	Input wr en i signal for this module.
rd_en_i	in	std_logic	Readback control or data signal for host-visible captured state.
data_in_i	in	std_logic_vector(DATA_WIDTH - 1 downto 0)	Input data in i signal for this module.
data_out_o	out	std_logic_vector(DATA_WIDTH - 1 downto 0)	Output data out o signal generated by this module.
wr_rdy_o	out	std_logic	Output wr rdy o signal generated by this module.
rd_rdy_o	out	std_logic	Readback control or data signal for host-visible captured state.
wr_valid_o	out	std_logic	Output valid qualifier aligned with the produced result.
rd_valid_o	out	std_logic	Readback control or data signal for host-visible captured state.
error_o	out	std_logic	Output error o signal generated by this module.
s_wr_addr_o	out	std_logic_vector((SLAVE_COUNT * ADDR_WIDTH) - 1 downto 0)	Output s wr addr o signal generated by this module.
s_rd_addr_o	out	std_logic_vector((SLAVE_COUNT * ADDR_WIDTH) - 1 downto 0)	Output s rd addr o signal generated by this module.
s_wr_en_o	out	std_logic_vector(SLAVE_COUNT - 1 downto 0)	Output s wr en o signal generated by this module.
s_rd_en_o	out	std_logic_vector(SLAVE_COUNT - 1 downto 0)	Output s rd en o signal generated by this module.
s_data_in_o	out	std_logic_vector((SLAVE_COUNT * DATA_WIDTH) - 1 downto 0)	Output s data in o signal generated by this module.
s_data_out_i	in	std_logic_vector((SLAVE_COUNT * DATA_WIDTH) - 1 downto 0)	Input s data out i signal for this module.
s_wr_rdy_i	in	std_logic_vector(SLAVE_COUNT - 1 downto 0)	Input s wr rdy i signal for this module.
s_rd_rdy_i	in	std_logic_vector(SLAVE_COUNT - 1 downto 0)	Input s rd rdy i signal for this module.
s_wr_valid_i	in	std_logic_vector(SLAVE_COUNT - 1 downto 0)	Input valid qualifier for this operation or sideband channel.
s_rd_valid_i	in	std_logic_vector(SLAVE_COUNT - 1 downto 0)	Input valid qualifier for this operation or sideband channel.
s_error_i	in	std_logic_vector(SLAVE_COUNT - 1 downto 0)	Input s error i signal for this module.

Register Interfaces

No fixed register map was found; this section documents the exposed register/control interface ports.

Interface	Directions	Signals	Representative ports
Register control/status	in, out	16	wr_addr_i, rd_addr_i, wr_en_i, rd_en_i, wr_rdy_o, rd_rdy_o, wr_valid_o, rd_valid_o, +8 more

Testbenches

tb_radif_reg_interconnect interface timing diagram

Source: interfaces/hdl/radif/testbenches/tb_radif_reg_interconnect.vhd

Self-checking or stimulus-focused testbench for reg interconnect. Exercises representative handshakes, reset behavior, frame boundaries, and numeric corner cases for regression runs.

Interface Timing Diagram

Source: interfaces/hdl/radif/testbenches/tb_radif_reg_interconnect.vhd

Horizontal Vertical

clk

rstn

rd_valid_o

s_rd_valid_i

s_wr_valid_i

wr_valid_o

data_in_i

data_out_o

rd_addr_i

s_data_in_o

s_data_out_i

s_rd_addr_o

s_wr_addr_o

wr_addr_i

error_o

rd_en_i

rd_rdy_o

s_error_i

s_rd_en_o

s_rd_rdy_i

s_wr_en_o

s_wr_rdy_i

wr_en_i

wr_rdy_o

Sources

interfaces/hdl/radif/src/radif_reg_interconnect.vhd