Use Cases
- Memory-mapped control/status integration with software-visible register maps.
Block Diagram
VHDL Include And Instantiation Template
File Header
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_regbank.all;Component Declaration
component radif_reg_bank is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
READ_ONLY_REG_COUNT : integer := 8;
READ_WRITE_REG_COUNT : integer := 64;
VENDOR_TAG : string := "XILINX";
PRODUCT_SERIES_TAG : string := "GENERIC"
);
port (
clk : in std_logic;
rstn : in std_logic;
wr_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
rd_addr : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
read_only_regs_i : in radif_reg_array_t(0 to READ_ONLY_REG_COUNT - 1)(DATA_WIDTH - 1 downto 0);
read_write_regs_o : out radif_reg_array_t(0 to READ_WRITE_REG_COUNT - 1)(DATA_WIDTH - 1 downto 0);
wr_rdy : out std_logic;
rd_rdy : out std_logic;
wr_valid : out std_logic;
rd_valid : out std_logic;
error : out std_logic
);
end component;Direct Entity Instantiation
u_radif_reg_bank : entity radhdl.radif_reg_bank
generic map (
DATA_WIDTH => 32,
ADDR_WIDTH => 16,
READ_ONLY_REG_COUNT => 8,
READ_WRITE_REG_COUNT => 64,
VENDOR_TAG => "XILINX",
PRODUCT_SERIES_TAG => "GENERIC"
)
port map (
clk => <clk_signal>,
rstn => <rstn_signal>,
wr_addr => <wr_addr_signal>,
rd_addr => <rd_addr_signal>,
wr_en => <wr_en_signal>,
rd_en => <rd_en_signal>,
data_in => <data_in_signal>,
data_out => <data_out_signal>,
read_only_regs_i => <read_only_regs_i_signal>,
read_write_regs_o => <read_write_regs_o_signal>,
wr_rdy => <wr_rdy_signal>,
rd_rdy => <rd_rdy_signal>,
wr_valid => <wr_valid_signal>,
rd_valid => <rd_valid_signal>,
error => <error_signal>
);Generics
| Name | Type | Default | Description |
|---|---|---|---|
| DATA_WIDTH | integer | 32 | Sets the bit width for DATA WIDTH values carried by this module. |
| ADDR_WIDTH | integer | 16 | Sets the bit width for ADDR WIDTH values carried by this module. |
| READ_ONLY_REG_COUNT | integer | 8 | Configures READ ONLY REG COUNT for this instance. |
| READ_WRITE_REG_COUNT | integer | 64 | Configures READ WRITE REG COUNT for this instance. |
| VENDOR_TAG | string | "XILINX" | Selects the vendor-specific implementation path, usually XILINX for DSP48/XPM-backed builds or generic for portable RTL. |
| PRODUCT_SERIES_TAG | string | "GENERIC" | Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
| clk | in | std_logic | Clock for the associated synchronous logic and handshake domain. |
| rstn | in | std_logic | Active-low reset for this clock domain. |
| wr_addr | in | std_logic_vector(ADDR_WIDTH - 1 downto 0) | Wr addr interface signal. |
| rd_addr | in | std_logic_vector(ADDR_WIDTH - 1 downto 0) | Readback control or data signal for host-visible captured state. |
| wr_en | in | std_logic | Wr en interface signal. |
| rd_en | in | std_logic | Readback control or data signal for host-visible captured state. |
| data_in | in | std_logic_vector(DATA_WIDTH - 1 downto 0) | Data in interface signal. |
| data_out | out | std_logic_vector(DATA_WIDTH - 1 downto 0) | Data out interface signal. |
| read_only_regs_i | in | radif_reg_array_t(0 to READ_ONLY_REG_COUNT - 1)(DATA_WIDTH - 1 downto 0) | Input read only regs i signal for this module. |
| read_write_regs_o | out | radif_reg_array_t(0 to READ_WRITE_REG_COUNT - 1)(DATA_WIDTH - 1 downto 0) | Output read write regs o signal generated by this module. |
| wr_rdy | out | std_logic | Wr rdy interface signal. |
| rd_rdy | out | std_logic | Readback control or data signal for host-visible captured state. |
| wr_valid | out | std_logic | Wr valid interface signal. |
| rd_valid | out | std_logic | Readback control or data signal for host-visible captured state. |
| error | out | std_logic | Error interface signal. |
Register Interfaces
No fixed register map was found; this section documents the exposed register/control interface ports.
| Interface | Directions | Signals | Representative ports |
|---|---|---|---|
| Register control/status | in, out | 8 | wr_addr, rd_addr, wr_en, rd_en, wr_rdy, rd_rdy, wr_valid, rd_valid |
Testbenches
tb_radif_axi_lite_to_reg
Self-checking or stimulus-focused testbench for axi lite to reg. Exercises representative handshakes, reset behavior, frame boundaries, and numeric corner cases for regression runs.
Interface Timing Diagram
tb_radif_reg_bank
Self-checking or stimulus-focused testbench for reg bank. Exercises representative handshakes, reset behavior, frame boundaries, and numeric corner cases for regression runs.
Interface Timing Diagram
tb_radif_reg_interconnect
Self-checking or stimulus-focused testbench for reg interconnect. Exercises representative handshakes, reset behavior, frame boundaries, and numeric corner cases for regression runs.
Interface Timing Diagram
tb_radif_smi16_to_reg
Self-checking or stimulus-focused testbench for smi16 to reg. Exercises representative handshakes, reset behavior, frame boundaries, and numeric corner cases for regression runs.
Interface Timing Diagram
Sources
- interfaces/hdl/radif/src/radif_reg_bank.vhd