Use Cases
- Memory-mapped control/status integration with software-visible register maps.
Block Diagram
VHDL Include And Instantiation Template
File Header
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_spi.all;Component Declaration
component radif_qspi_slave_to_reg is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 16;
ENABLE_QUAD_DATA : boolean := true;
ENABLE_CRC16 : boolean := false;
VENDOR_TAG : string := "XILINX";
PRODUCT_SERIES_TAG : string := "GENERIC"
);
port (
clk : in std_logic;
rstn : in std_logic;
qspi_sclk_i : in std_logic;
qspi_cs_n_i : in std_logic;
qspi_io_i : in std_logic_vector(3 downto 0);
qspi_io_o : out std_logic_vector(3 downto 0);
qspi_io_oen : out std_logic_vector(3 downto 0);
reg_wr_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
reg_rd_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
reg_wr_en : out std_logic;
reg_rd_en : out std_logic;
reg_data_in : out std_logic_vector(DATA_WIDTH - 1 downto 0);
reg_data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0);
reg_wr_rdy : in std_logic;
reg_rd_rdy : in std_logic;
reg_wr_valid : in std_logic;
reg_rd_valid : in std_logic;
reg_error : in std_logic
);
end component;Direct Entity Instantiation
u_radif_qspi_slave_to_reg : entity radhdl.radif_qspi_slave_to_reg
generic map (
DATA_WIDTH => 32,
ADDR_WIDTH => 16,
ENABLE_QUAD_DATA => true,
ENABLE_CRC16 => false,
VENDOR_TAG => "XILINX",
PRODUCT_SERIES_TAG => "GENERIC"
)
port map (
clk => <clk_signal>,
rstn => <rstn_signal>,
qspi_sclk_i => <qspi_sclk_i_signal>,
qspi_cs_n_i => <qspi_cs_n_i_signal>,
qspi_io_i => <qspi_io_i_signal>,
qspi_io_o => <qspi_io_o_signal>,
qspi_io_oen => <qspi_io_oen_signal>,
reg_wr_addr => <reg_wr_addr_signal>,
reg_rd_addr => <reg_rd_addr_signal>,
reg_wr_en => <reg_wr_en_signal>,
reg_rd_en => <reg_rd_en_signal>,
reg_data_in => <reg_data_in_signal>,
reg_data_out => <reg_data_out_signal>,
reg_wr_rdy => <reg_wr_rdy_signal>,
reg_rd_rdy => <reg_rd_rdy_signal>,
reg_wr_valid => <reg_wr_valid_signal>,
reg_rd_valid => <reg_rd_valid_signal>,
reg_error => <reg_error_signal>
);Generics
| Name | Type | Default | Description |
|---|---|---|---|
| DATA_WIDTH | integer | 32 | Sets the bit width for DATA WIDTH values carried by this module. |
| ADDR_WIDTH | integer | 16 | Sets the bit width for ADDR WIDTH values carried by this module. |
| ENABLE_QUAD_DATA | boolean | true | Configures ENABLE QUAD DATA for this instance. |
| ENABLE_CRC16 | boolean | false | Configures ENABLE CRC16 for this instance. |
| VENDOR_TAG | string | "XILINX" | Selects the vendor-specific implementation path, usually XILINX for DSP48/XPM-backed builds or generic for portable RTL. |
| PRODUCT_SERIES_TAG | string | "GENERIC" | Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior. |
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
| clk | in | std_logic | Clock for the associated synchronous logic and handshake domain. |
| rstn | in | std_logic | Active-low reset for this clock domain. |
| qspi_sclk_i | in | std_logic | Input qspi sclk i signal for this module. |
| qspi_cs_n_i | in | std_logic | Input qspi cs n i signal for this module. |
| qspi_io_i | in | std_logic_vector(3 downto 0) | Input qspi io i signal for this module. |
| qspi_io_o | out | std_logic_vector(3 downto 0) | Output qspi io o signal generated by this module. |
| qspi_io_oen | out | std_logic_vector(3 downto 0) | Qspi io oen interface signal. |
| reg_wr_addr | out | std_logic_vector(ADDR_WIDTH - 1 downto 0) | Register write address issued to the internal RadIF register target. |
| reg_rd_addr | out | std_logic_vector(ADDR_WIDTH - 1 downto 0) | Register read address issued to the internal RadIF register target. |
| reg_wr_en | out | std_logic | One-cycle write request pulse for the internal register target. |
| reg_rd_en | out | std_logic | One-cycle read request pulse for the internal register target. |
| reg_data_in | out | std_logic_vector(DATA_WIDTH - 1 downto 0) | Write data presented to the internal register target. |
| reg_data_out | in | std_logic_vector(DATA_WIDTH - 1 downto 0) | Read data returned by the internal register target. |
| reg_wr_rdy | in | std_logic | Write-side ready indication from the internal register target. |
| reg_rd_rdy | in | std_logic | Read-side ready indication from the internal register target. |
| reg_wr_valid | in | std_logic | Write response valid indication from the internal register target. |
| reg_rd_valid | in | std_logic | Read response valid indication from the internal register target. |
| reg_error | in | std_logic | Register target error flag converted into the external bus error response. |
Register Interfaces
No fixed register map was found; this section documents the exposed register/control interface ports.
| Interface | Directions | Signals | Representative ports |
|---|---|---|---|
| Register control/status | in, out | 11 | reg_wr_addr, reg_rd_addr, reg_wr_en, reg_rd_en, reg_data_in, reg_data_out, reg_wr_rdy, reg_rd_rdy, +3 more |
Testbenches
tb_radif_interfaces_smoke
Interface elaboration and idle-state smoke testbench. This bench instantiates the RADIF SPI, QSPI, I2C, DMA, and SPI-to-AXI blocks together to catch compile/elaboration issues and verify reset-idle behavior for shared interface wrappers. It intentionally does not drive complete bus transactions; it checks that inactive SPI/QSPI pins remain tri-stated after reset. Use the module-specific testbenches for transaction waveforms.
Interface Timing Diagram
QSPI interface signals
QSPI Interface Waveform
Sources
- interfaces/hdl/radif/src/radif_qspi_slave_to_reg.vhd