radif_irq_controller

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_regbank.all;

Component Declaration

component radif_irq_controller is
  generic (
    DATA_WIDTH : integer := 32;
    REG_ADDR_WIDTH : integer := 16;
    IRQ_COUNT : positive := 8;
    VENDOR_TAG : string := "GENERIC";
    PRODUCT_SERIES_TAG : string := "GENERIC"
  );
  port (
    clk : in std_logic;
    rstn : in std_logic;
    irq_i : in std_logic_vector(IRQ_COUNT - 1 downto 0);
    irq_o : out std_logic;
    irq_pending_o : out std_logic_vector(IRQ_COUNT - 1 downto 0);
    reg_wr_addr : in std_logic_vector(REG_ADDR_WIDTH - 1 downto 0);
    reg_rd_addr : in std_logic_vector(REG_ADDR_WIDTH - 1 downto 0);
    reg_wr_en : in std_logic;
    reg_rd_en : in std_logic;
    reg_data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_wr_rdy : out std_logic;
    reg_rd_rdy : out std_logic;
    reg_wr_valid : out std_logic;
    reg_rd_valid : out std_logic;
    reg_error : out std_logic
  );
end component;

Direct Entity Instantiation

u_radif_irq_controller : entity radhdl.radif_irq_controller
  generic map (
    DATA_WIDTH         => 32,
    REG_ADDR_WIDTH     => 16,
    IRQ_COUNT          => 8,
    VENDOR_TAG         => "GENERIC",
    PRODUCT_SERIES_TAG => "GENERIC"
  )
  port map (
    clk           => <clk_signal>,
    rstn          => <rstn_signal>,
    irq_i         => <irq_i_signal>,
    irq_o         => <irq_o_signal>,
    irq_pending_o => <irq_pending_o_signal>,
    reg_wr_addr   => <reg_wr_addr_signal>,
    reg_rd_addr   => <reg_rd_addr_signal>,
    reg_wr_en     => <reg_wr_en_signal>,
    reg_rd_en     => <reg_rd_en_signal>,
    reg_data_in   => <reg_data_in_signal>,
    reg_data_out  => <reg_data_out_signal>,
    reg_wr_rdy    => <reg_wr_rdy_signal>,
    reg_rd_rdy    => <reg_rd_rdy_signal>,
    reg_wr_valid  => <reg_wr_valid_signal>,
    reg_rd_valid  => <reg_rd_valid_signal>,
    reg_error     => <reg_error_signal>
  );