radif_gpio_reg_block Datasheet

Use Cases

Memory-mapped control/status integration with software-visible register maps.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_regbank.all;

Component Declaration

component radif_gpio_reg_block is
  generic (
    DATA_WIDTH : integer := 32;
    REG_ADDR_WIDTH : integer := 16;
    GPIO_WIDTH : positive := 8;
    RESET_OUT_VALUE : std_logic_vector(GPIO_WIDTH - 1 downto 0) := (others => '0');
    RESET_OUT_ENABLE : std_logic_vector(GPIO_WIDTH - 1 downto 0) := (others => '0');
    VENDOR_TAG : string := "GENERIC";
    PRODUCT_SERIES_TAG : string := "GENERIC"
  );
  port (
    clk : in std_logic;
    rstn : in std_logic;
    gpio_i : in std_logic_vector(GPIO_WIDTH - 1 downto 0);
    gpio_o : out std_logic_vector(GPIO_WIDTH - 1 downto 0);
    gpio_oe_o : out std_logic_vector(GPIO_WIDTH - 1 downto 0);
    irq_o : out std_logic;
    reg_wr_addr : in std_logic_vector(REG_ADDR_WIDTH - 1 downto 0);
    reg_rd_addr : in std_logic_vector(REG_ADDR_WIDTH - 1 downto 0);
    reg_wr_en : in std_logic;
    reg_rd_en : in std_logic;
    reg_data_in : in std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0);
    reg_wr_rdy : out std_logic;
    reg_rd_rdy : out std_logic;
    reg_wr_valid : out std_logic;
    reg_rd_valid : out std_logic;
    reg_error : out std_logic
  );
end component;

Direct Entity Instantiation

u_radif_gpio_reg_block : entity radhdl.radif_gpio_reg_block
  generic map (
    DATA_WIDTH         => 32,
    REG_ADDR_WIDTH     => 16,
    GPIO_WIDTH         => 8,
    RESET_OUT_VALUE    => (others => '0'),
    RESET_OUT_ENABLE   => (others => '0'),
    VENDOR_TAG         => "GENERIC",
    PRODUCT_SERIES_TAG => "GENERIC"
  )
  port map (
    clk          => <clk_signal>,
    rstn         => <rstn_signal>,
    gpio_i       => <gpio_i_signal>,
    gpio_o       => <gpio_o_signal>,
    gpio_oe_o    => <gpio_oe_o_signal>,
    irq_o        => <irq_o_signal>,
    reg_wr_addr  => <reg_wr_addr_signal>,
    reg_rd_addr  => <reg_rd_addr_signal>,
    reg_wr_en    => <reg_wr_en_signal>,
    reg_rd_en    => <reg_rd_en_signal>,
    reg_data_in  => <reg_data_in_signal>,
    reg_data_out => <reg_data_out_signal>,
    reg_wr_rdy   => <reg_wr_rdy_signal>,
    reg_rd_rdy   => <reg_rd_rdy_signal>,
    reg_wr_valid => <reg_wr_valid_signal>,
    reg_rd_valid => <reg_rd_valid_signal>,
    reg_error    => <reg_error_signal>
  );

Generics

Name	Type	Default	Description
DATA_WIDTH	integer	32	Width of the RADIF register data path.
REG_ADDR_WIDTH	integer	16	Width of the RADIF byte address path.
GPIO_WIDTH	positive	8	Number of GPIO pins controlled or observed by this block.
RESET_OUT_VALUE	std_logic_vector(GPIO_WIDTH - 1 downto 0)	(others => '0')	Reset value for GPIO outputs.
RESET_OUT_ENABLE	std_logic_vector(GPIO_WIDTH - 1 downto 0)	(others => '0')	Reset value for GPIO output enables.
VENDOR_TAG	string	"GENERIC"	Vendor selector retained for generated package consistency.
PRODUCT_SERIES_TAG	string	"GENERIC"	Device-family selector retained for generated package consistency.

Ports

Name	Direction	Type	Description
clk	in	std_logic	Register clock.
rstn	in	std_logic	Active-low register reset.
gpio_i	in	std_logic_vector(GPIO_WIDTH - 1 downto 0)	External GPIO input pins synchronized into clk.
gpio_o	out	std_logic_vector(GPIO_WIDTH - 1 downto 0)	GPIO output drive values.
gpio_oe_o	out	std_logic_vector(GPIO_WIDTH - 1 downto 0)	GPIO output enable bits.
irq_o	out	std_logic	Interrupt asserted when an enabled edge-detect pending bit is set.
reg_wr_addr	in	std_logic_vector(REG_ADDR_WIDTH - 1 downto 0)	Register write address.
reg_rd_addr	in	std_logic_vector(REG_ADDR_WIDTH - 1 downto 0)	Register read address.
reg_wr_en	in	std_logic	One-cycle register write request.
reg_rd_en	in	std_logic	One-cycle register read request.
reg_data_in	in	std_logic_vector(DATA_WIDTH - 1 downto 0)	Register write data.
reg_data_out	out	std_logic_vector(DATA_WIDTH - 1 downto 0)	Register read data.
reg_wr_rdy	out	std_logic	Register write ready.
reg_rd_rdy	out	std_logic	Register read ready.
reg_wr_valid	out	std_logic	Register write response valid.
reg_rd_valid	out	std_logic	Register read response valid.
reg_error	out	std_logic	Register transaction error.

Measured Implementation Metrics

Metrics are generated by RadBuild from real Vivado synthesis reports for representative device targets. Raw report paths are preserved in the checked summary JSON.

Part	Clock ns	MHz	LUTs	FFs	BRAM tiles	DSPs	Setup WNS ns	Hold WHS ns	Generics	Summary
xc7z020clg400-1	10.0	100.0	75	83	0	0	6.88	0.152	-	projects/synth_reports/radif_gpio_reg_block/xc7z020clg400-1/synth_summary.json
xczu3eg-sfvc784-1-e	6.667	149.993	75	83	0	0	5.707	-0.059	-	projects/synth_reports/radif_gpio_reg_block/xczu3eg-sfvc784-1-e/synth_summary.json

Register Interfaces

Static register maps are rendered below for this module.

Interface	Directions	Signals	Representative ports
Register control/status	in, out	11	reg_wr_addr, reg_rd_addr, reg_wr_en, reg_rd_en, reg_data_in, reg_data_out, reg_wr_rdy, reg_rd_rdy, +3 more

Register Maps

radif_gpio_reg_block

Source: interfaces/hdl/radif/register_maps/radif_gpio_reg_block.map.json

Controls GPIO output values, output enables, input readback, edge detection, and interrupt masking.

Register	Offset	Access	Reset	Description
out_value	0x00	rw	RESET_OUT_VALUE	GPIO output drive values.
out_enable	0x04	rw	RESET_OUT_ENABLE	GPIO output enable controls.
in_value	0x08	ro	0x00000000	Synchronized GPIO input values.
irq_status	0x0C	rw1c	0x00000000	Latched GPIO edge-detect interrupt pending bits.
irq_mask	0x10	rw	0x00000000	GPIO interrupt enable mask.
rise_enable	0x14	rw	0x00000000	Rising-edge interrupt detection enable bits.
fall_enable	0x18	rw	0x00000000	Falling-edge interrupt detection enable bits.

out_value

Offset 0x00 / Access rw / Reset RESET_OUT_VALUE

GPIO output drive values.

OutValue[15:0]

1514131211109876543210

GPIO OUT [15:0]

OutValue[31:16]

31302928272625242322212019181716

GPIO OUT [31:16]

Name	Register bit(s)	Description
GPIO OUT	OutValue[31:0]	One output value bit per GPIO pin. Bits above GPIO_WIDTH are unused.

out_enable

Offset 0x04 / Access rw / Reset RESET_OUT_ENABLE

GPIO output enable controls.

OutEnable[15:0]

1514131211109876543210

GPIO OE [15:0]

OutEnable[31:16]

31302928272625242322212019181716

GPIO OE [31:16]

Name	Register bit(s)	Description
GPIO OE	OutEnable[31:0]	One output-enable bit per GPIO pin. Bits above GPIO_WIDTH are unused.

in_value

Offset 0x08 / Access ro / Reset 0x00000000

Synchronized GPIO input values.

InValue[15:0]

1514131211109876543210

GPIO IN [15:0]

InValue[31:16]

31302928272625242322212019181716

GPIO IN [31:16]

Name	Register bit(s)	Description
GPIO IN	InValue[31:0]	One synchronized input value bit per GPIO pin. Bits above GPIO_WIDTH read as zero.

irq_status

Offset 0x0C / Access rw1c / Reset 0x00000000

Latched GPIO edge-detect interrupt pending bits.

IrqStatus[15:0]

1514131211109876543210

IRQ PENDING [15:0]

IrqStatus[31:16]

31302928272625242322212019181716

IRQ PENDING [31:16]

Name	Register bit(s)	Description
IRQ PENDING	IrqStatus[31:0]	Pending edge bits. Write 1 to clear the corresponding pending bit.

irq_mask

Offset 0x10 / Access rw / Reset 0x00000000

GPIO interrupt enable mask.

IrqMask[15:0]

1514131211109876543210

IRQ MASK [15:0]

IrqMask[31:16]

31302928272625242322212019181716

IRQ MASK [31:16]

Name	Register bit(s)	Description
IRQ MASK	IrqMask[31:0]	A bit value of 1 allows the corresponding pending bit to assert irq_o.

rise_enable

Offset 0x14 / Access rw / Reset 0x00000000

Rising-edge interrupt detection enable bits.

RiseEnable[15:0]

1514131211109876543210

RISE EN [15:0]

RiseEnable[31:16]

31302928272625242322212019181716

RISE EN [31:16]

Name	Register bit(s)	Description
RISE EN	RiseEnable[31:0]	A bit value of 1 latches a pending interrupt when the corresponding GPIO input rises.

fall_enable

Offset 0x18 / Access rw / Reset 0x00000000

Falling-edge interrupt detection enable bits.

FallEnable[15:0]

1514131211109876543210

FALL EN [15:0]

FallEnable[31:16]

31302928272625242322212019181716

FALL EN [31:16]

Name	Register bit(s)	Description
FALL EN	FallEnable[31:0]	A bit value of 1 latches a pending interrupt when the corresponding GPIO input falls.

Testbenches

tb_radif_gpio_irq interface timing diagram

Source: interfaces/hdl/radif/testbenches/tb_radif_gpio_irq.vhd

Exercises RADIF GPIO and interrupt-controller register behavior.

Interface Timing Diagram

Source: interfaces/hdl/radif/testbenches/tb_radif_gpio_irq.vhd

Horizontal Vertical

clk

rstn

irq_o

reg_rd_valid

reg_wr_valid

reg_data_in

reg_data_out

reg_rd_addr

reg_wr_addr

gpio_i

gpio_o

gpio_oe_o

reg_error

reg_rd_en

reg_rd_rdy

reg_wr_en

reg_wr_rdy

Sources

interfaces/hdl/radif/src/radif_gpio_reg_block.vhd