radif_axi4_axis_dma

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.interfaces.all;
-- Narrower alternative: use radhdl.interfaces_axi.all;

Component Declaration

component radif_axi4_axis_dma is
  generic (
    REG_DATA_WIDTH : integer := 32;
    REG_ADDR_WIDTH : integer := 16;
    AXI_ADDR_WIDTH : integer := 32;
    AXI_DATA_WIDTH : integer := 32;
    AXIS_DATA_WIDTH : integer := 32;
    ENABLE_MM2S : boolean := true;
    ENABLE_S2MM : boolean := true;
    FIFO_DEPTH : integer := 1024;
    FIFO_FWFT : boolean := true;
    MAX_BURST_LEN : integer := 16;
    VENDOR_TAG : string := "XILINX";
    PRODUCT_SERIES_TAG : string := "GENERIC"
  );
  port (
    m_axis_tdata : out std_logic_vector(AXIS_DATA_WIDTH - 1 downto 0);
    m_axis_tvalid : out std_logic;
    m_axis_tready : in std_logic;
    m_axis_tlast : out std_logic;
    s_axis_tdata : in std_logic_vector(AXIS_DATA_WIDTH - 1 downto 0);
    s_axis_tvalid : in std_logic;
    s_axis_tready : out std_logic;
    s_axis_tlast : in std_logic;
    m_axi_awaddr : out std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0);
    m_axi_awlen : out std_logic_vector(7 downto 0);
    m_axi_awsize : out std_logic_vector(2 downto 0);
    m_axi_awburst : out std_logic_vector(1 downto 0);
    m_axi_awvalid : out std_logic;
    m_axi_awready : in std_logic;
    m_axi_wdata : out std_logic_vector(AXI_DATA_WIDTH - 1 downto 0);
    m_axi_wstrb : out std_logic_vector((AXI_DATA_WIDTH / 8) - 1 downto 0);
    m_axi_wlast : out std_logic;
    m_axi_wvalid : out std_logic;
    m_axi_wready : in std_logic;
    m_axi_bresp : in std_logic_vector(1 downto 0);
    m_axi_bvalid : in std_logic;
    m_axi_bready : out std_logic;
    m_axi_araddr : out std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0);
    m_axi_arlen : out std_logic_vector(7 downto 0);
    m_axi_arsize : out std_logic_vector(2 downto 0);
    m_axi_arburst : out std_logic_vector(1 downto 0);
    m_axi_arvalid : out std_logic;
    m_axi_arready : in std_logic;
    m_axi_rdata : in std_logic_vector(AXI_DATA_WIDTH - 1 downto 0);
    m_axi_rresp : in std_logic_vector(1 downto 0);
    m_axi_rlast : in std_logic;
    m_axi_rvalid : in std_logic;
    m_axi_rready : out std_logic;
    clk : in std_logic;
    rstn : in std_logic;
    reg_wr_addr : in std_logic_vector(REG_ADDR_WIDTH - 1 downto 0);
    reg_rd_addr : in std_logic_vector(REG_ADDR_WIDTH - 1 downto 0);
    reg_wr_en : in std_logic;
    reg_rd_en : in std_logic;
    reg_data_in : in std_logic_vector(REG_DATA_WIDTH - 1 downto 0);
    reg_data_out : out std_logic_vector(REG_DATA_WIDTH - 1 downto 0);
    reg_wr_rdy : out std_logic;
    reg_rd_rdy : out std_logic;
    reg_wr_valid : out std_logic;
    reg_rd_valid : out std_logic;
    reg_error : out std_logic;
    irq_o : out std_logic
  );
end component;

Direct Entity Instantiation

u_radif_axi4_axis_dma : entity radhdl.radif_axi4_axis_dma
  generic map (
    REG_DATA_WIDTH     => 32,
    REG_ADDR_WIDTH     => 16,
    AXI_ADDR_WIDTH     => 32,
    AXI_DATA_WIDTH     => 32,
    AXIS_DATA_WIDTH    => 32,
    ENABLE_MM2S        => true,
    ENABLE_S2MM        => true,
    FIFO_DEPTH         => 1024,
    FIFO_FWFT          => true,
    MAX_BURST_LEN      => 16,
    VENDOR_TAG         => "XILINX",
    PRODUCT_SERIES_TAG => "GENERIC"
  )
  port map (
    m_axis_tdata  => <m_axis_tdata_signal>,
    m_axis_tvalid => <m_axis_tvalid_signal>,
    m_axis_tready => <m_axis_tready_signal>,
    m_axis_tlast  => <m_axis_tlast_signal>,
    s_axis_tdata  => <s_axis_tdata_signal>,
    s_axis_tvalid => <s_axis_tvalid_signal>,
    s_axis_tready => <s_axis_tready_signal>,
    s_axis_tlast  => <s_axis_tlast_signal>,
    m_axi_awaddr  => <m_axi_awaddr_signal>,
    m_axi_awlen   => <m_axi_awlen_signal>,
    m_axi_awsize  => <m_axi_awsize_signal>,
    m_axi_awburst => <m_axi_awburst_signal>,
    m_axi_awvalid => <m_axi_awvalid_signal>,
    m_axi_awready => <m_axi_awready_signal>,
    m_axi_wdata   => <m_axi_wdata_signal>,
    m_axi_wstrb   => <m_axi_wstrb_signal>,
    m_axi_wlast   => <m_axi_wlast_signal>,
    m_axi_wvalid  => <m_axi_wvalid_signal>,
    m_axi_wready  => <m_axi_wready_signal>,
    m_axi_bresp   => <m_axi_bresp_signal>,
    m_axi_bvalid  => <m_axi_bvalid_signal>,
    m_axi_bready  => <m_axi_bready_signal>,
    m_axi_araddr  => <m_axi_araddr_signal>,
    m_axi_arlen   => <m_axi_arlen_signal>,
    m_axi_arsize  => <m_axi_arsize_signal>,
    m_axi_arburst => <m_axi_arburst_signal>,
    m_axi_arvalid => <m_axi_arvalid_signal>,
    m_axi_arready => <m_axi_arready_signal>,
    m_axi_rdata   => <m_axi_rdata_signal>,
    m_axi_rresp   => <m_axi_rresp_signal>,
    m_axi_rlast   => <m_axi_rlast_signal>,
    m_axi_rvalid  => <m_axi_rvalid_signal>,
    m_axi_rready  => <m_axi_rready_signal>,
    clk           => <clk_signal>,
    rstn          => <rstn_signal>,
    reg_wr_addr   => <reg_wr_addr_signal>,
    reg_rd_addr   => <reg_rd_addr_signal>,
    reg_wr_en     => <reg_wr_en_signal>,
    reg_rd_en     => <reg_rd_en_signal>,
    reg_data_in   => <reg_data_in_signal>,
    reg_data_out  => <reg_data_out_signal>,
    reg_wr_rdy    => <reg_wr_rdy_signal>,
    reg_rd_rdy    => <reg_rd_rdy_signal>,
    reg_wr_valid  => <reg_wr_valid_signal>,
    reg_rd_valid  => <reg_rd_valid_signal>,
    reg_error     => <reg_error_signal>,
    irq_o         => <irq_o_signal>
  );