raddsp_xilinx_dsp48_square

Use Cases

Reusable FPGA DSP pipelines that need fixed-point, timing-aware implementation.

Block Diagram

VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_xilinx_dsp48_square_seq is
  generic (
    DEVICE_FAMILY : string := "7series";
    WIDTH : positive := 32
  );
  port (
    clk : in std_logic;
    rst : in std_logic;
    start_i : in std_logic;
    x_i : in signed(WIDTH - 1 downto 0);
    busy_o : out std_logic;
    valid_o : out std_logic;
    y_o : out unsigned((2 * WIDTH) - 1 downto 0)
  );
end component;

Direct Entity Instantiation

u_raddsp_xilinx_dsp48_square_seq : entity radhdl.raddsp_xilinx_dsp48_square_seq
  generic map (
    DEVICE_FAMILY => "7series",
    WIDTH         => 32
  )
  port map (
    clk     => <clk_signal>,
    rst     => <rst_signal>,
    start_i => <start_i_signal>,
    x_i     => <x_i_signal>,
    busy_o  => <busy_o_signal>,
    valid_o => <valid_o_signal>,
    y_o     => <y_o_signal>
  );

Generics

Name	Type	Default	Description
DEVICE_FAMILY	string	"7series"	Identifies the target FPGA family so wrappers can choose the correct primitive or conservative portable behavior.
WIDTH	positive	32	Sets the bit width for WIDTH values carried by this module.

Ports

Name	Direction	Type	Description
clk	in	std_logic	Clock for the associated synchronous logic and handshake domain.
rst	in	std_logic	Active-high synchronous reset for this clock domain.
start_i	in	std_logic	Input start i signal for this module.
x_i	in	signed(WIDTH - 1 downto 0)	Input x i signal for this module.
busy_o	out	std_logic	Output busy o signal generated by this module.
valid_o	out	std_logic	Output valid qualifier aligned with the produced result.
y_o	out	unsigned((2 * WIDTH) - 1 downto 0)	Output y o signal generated by this module.

Testbenches

No directly associated testbench was found.

Sources

dsp/hdl/raddsp/src/raddsp_xilinx_dsp48_square_seq.vhd