Use Cases
- Reusable FPGA DSP pipelines that need fixed-point, timing-aware implementation.
Block Diagram
VHDL Include And Instantiation Template
File Header
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;Component Declaration
component raddsp_gowin_multalu27x32_mul is
port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
a_i : in std_logic_vector(26 downto 0);
b_i : in std_logic_vector(31 downto 0);
p_o : out std_logic_vector(63 downto 0)
);
end component;Direct Entity Instantiation
u_raddsp_gowin_multalu27x32_mul : entity radhdl.raddsp_gowin_multalu27x32_mul
port map (
clk => <clk_signal>,
rst => <rst_signal>,
ce => <ce_signal>,
a_i => <a_i_signal>,
b_i => <b_i_signal>,
p_o => <p_o_signal>
);Generics
No generics declared.
Ports
| Name | Direction | Type | Description |
|---|---|---|---|
| clk | in | std_logic | |
| rst | in | std_logic | |
| ce | in | std_logic | |
| a_i | in | std_logic_vector(26 downto 0) | |
| b_i | in | std_logic_vector(31 downto 0) | |
| p_o | out | std_logic_vector(63 downto 0) |
Testbenches
No directly associated testbench was found.
Sources
- dsp/hdl/raddsp/src/raddsp_gowin_multalu27x32_mul.vhd
