Radical Computer Technologies
DSP / entity

raddsp_gowin_multalu27x32_mul

Documentation version: 0.2.0 / Subpackage: dsp_transform / Source package: raddsp

Signed 27x32 multiply built from two Gowin GW5A MULTALU27X18 blocks. The coefficient operand is split as signed high 18 bits plus unsigned low 14 bits, preserving exact two's-complement reconstruction: b32 = signed(b31:14) * 2^14 + unsigned(b13:0)

Use Cases

Block Diagram

raddsp_gowin_multalu27x32_mul radhdl entity clk rst ce a_i b_i p_o
VHDL Include And Instantiation Template

File Header

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library radhdl;
-- Direct entity instantiation below does not require importing the entity name.
use radhdl.dsp.all;
-- Narrower alternative: use radhdl.dsp_transform.all;

Component Declaration

component raddsp_gowin_multalu27x32_mul is
  port (
    clk : in std_logic;
    rst : in std_logic;
    ce : in std_logic;
    a_i : in std_logic_vector(26 downto 0);
    b_i : in std_logic_vector(31 downto 0);
    p_o : out std_logic_vector(63 downto 0)
  );
end component;

Direct Entity Instantiation

u_raddsp_gowin_multalu27x32_mul : entity radhdl.raddsp_gowin_multalu27x32_mul
  port map (
    clk => <clk_signal>,
    rst => <rst_signal>,
    ce  => <ce_signal>,
    a_i => <a_i_signal>,
    b_i => <b_i_signal>,
    p_o => <p_o_signal>
  );

Generics

No generics declared.

Ports

NameDirectionTypeDescription
clkinstd_logic
rstinstd_logic
ceinstd_logic
a_iinstd_logic_vector(26 downto 0)
b_iinstd_logic_vector(31 downto 0)
p_ooutstd_logic_vector(63 downto 0)

Testbenches

No directly associated testbench was found.

Sources